Merge tag 'mesa-23.3.3' into lineage-18.1

mesa-23.3.3

VERSION

@@ -1 +1 @@
-23.3.2
+23.3.3

docs/relnotes.rst

@@ -3,6 +3,7 @@ Release Notes
 
 The release notes summarize what's new or changed in each Mesa release.
 
+-  :doc:`23.3.3 release notes <relnotes/23.3.3>`
 -  :doc:`23.3.2 release notes <relnotes/23.3.2>`
 -  :doc:`23.3.1 release notes <relnotes/23.3.1>`
 -  :doc:`23.3.0 release notes <relnotes/23.3.0>`
@@ -405,6 +406,7 @@ The release notes summarize what's new or changed in each Mesa release.
    :maxdepth: 1
    :hidden:
 
+   23.3.3 <relnotes/23.3.3>
    23.3.2 <relnotes/23.3.2>
    23.3.1 <relnotes/23.3.1>
    23.3.0 <relnotes/23.3.0>

docs/relnotes/23.3.2.rst

@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-    TBD.
+    3cfcb81fa16f89c56abe3855d2637d396ee4e03849b659000a6b8e5f57e69adc  mesa-23.3.2.tar.xz
 
 
 New features

docs/relnotes/23.3.3.rst

@@ -0,0 +1,155 @@
+Mesa 23.3.3 Release Notes / 2024-01-10
+======================================
+
+Mesa 23.3.3 is a bug fix release which fixes bugs found since the 23.3.2 release.
+
+Mesa 23.3.3 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 23.3.3 implements the Vulkan 1.3 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+    TBD.
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- Error during SPIR-V parsing of OpCopyLogical
+- radv: Atlas Fallen corrupted rendering
+- intel: Require 64KB alignment when using CCS and multiple engines
+- 23.3.2 regression: kms_swrast_dri.so segfaults
+- Mesa is not compatible with Python 3.12 due to use of distutils
+- anv: importing memory for a compressed image using modifier is hitting an assert
+
+
+Changes
+-------
+
+Connor Abbott (1):
+
+- ir3/legalize: Fix helper propagation with b.any/b.all/getone
+
+Daniel Schürmann (1):
+
+- nir/opt_move_discards_to_top: don't schedule discard/demote across subgroup operations
+
+Dave Airlie (5):
+
+- gallivm: handle llvm 16 atexit ordering problems.
+- intel/compiler: fix release build unused variable.
+- llvmpipe: fix caching for texture shaders.
+- intel/compiler: reemit boolean resolve for inverted if on gen5
+- radv: don't emit cp dma packets on video rings.
+
+Eric Engestrom (13):
+
+- docs: add sha256sum for 23.3.2
+- .pick_status.json: Mark eb5bb5c784e97c533e30b348e82e446ac0da59c8 as denominated
+- .pick_status.json: Update to ebee672ef87794f3f4201270623a92f34e62b8ff
+- .pick_status.json: Mark 060439bdf0e74f0f2e255d0a81b5356f9a2f5457 as denominated
+- .pick_status.json: Mark 8d0e70f628b745ad81124e0c3fe5e46ea84f6b46 as denominated
+- .pick_status.json: Update to 39c8cca34fb72db055df18abf1d473e099f4b05b
+- .pick_status.json: Update to 2c078bfd18cae0ed1a0a3916020e49fb74668504
+- .pick_status.json: Update to e2a7c877ad1fd6bda4032f707eea7646e5229969
+- .pick_status.json: Update to 031978933151e95690e93919e7bfd9f1753f2794
+- .pick_status.json: Mark fbe4e16db2d369c3e54067d17f81bdce8661a461 as denominated
+- .pick_status.json: Mark b38c776690c9c39b04c57d74f9b036de56995aff as denominated
+- .pick_status.json: Update to f6d2df5a7542025022e69b81dbe3af3e51ea5cd3
+- .pick_status.json: Update to 67ad1142cf6afe61de834cefeddb4be06382899f
+
+Erik Faye-Lund (2):
+
+- zink: update profile schema
+- zink: use KHR version of maint5 features
+
+Friedrich Vock (1):
+
+- radv/rt: Free traversal NIR after compilation
+
+Georg Lehmann (1):
+
+- aco: fix applying input modifiers to DPP8
+
+Jonathan Gray (1):
+
+- zink: put sysmacros.h include under #ifdef MAJOR_IN_SYSMACROS
+
+José Roberto de Souza (2):
+
+- anv: Assume that imported bos already have flat CCS requirements satisfied
+- anv: Increase ANV_MAX_QUEUE_FAMILIES
+
+Karol Herbst (2):
+
+- zink: lock screen queue on context_destroy and CreateSwapchain
+- zink: fix heap-use-after-free on batch_state with sub-allocated pipe_resources
+
+Konstantin Seurer (2):
+
+- vtn: Remove transpose(m0)*m1 fast path
+- vtn: Allow for OpCopyLogical with different but compatible types
+
+Leo Liu (1):
+
+- gallium/vl: match YUYV/UYVY swizzle with change of color channels
+
+Lionel Landwerlin (2):
+
+- isl: implement Wa_22015614752
+- intel/fs: fix depth compute state for unchanged depth layout
+
+Marek Olšák (1):
+
+- glthread: don't unroll draws using user VBOs with GLES
+
+Mary Guillemard (2):
+
+- zink: Initialize pQueueFamilyIndices for image query / create
+- zink: Always fill external_only in zink_query_dmabuf_modifiers
+
+Mike Blumenkrantz (1):
+
+- zink: enforce maxTexelBufferElements for texel buffer sizing
+
+Rhys Perry (1):
+
+- aco/tests: use more raw strings
+
+Samuel Pitoiset (2):
+
+- radv: fix binding partial depth/stencil views with dynamic rendering
+- radv: disable stencil test without a stencil attachment
+
+Sil Vilerino (2):
+
+- Revert "d3d12: Only destroy the winsys during screen destruction, not reset"
+- Revert "d3d12: Fix screen->winsys leak in d3d12_screen"
+
+Vinson Lee (1):
+
+- ac/rgp: Fix single-bit-bitfield-constant-conversion warning
+
+Yonggang Luo (1):
+
+- meson: Support for both packaging and distutils
+
+antonino (1):
+
+- egl: only check dri3 on X11

meson.build

@@ -886,9 +886,12 @@ prog_python = import('python').find_installation('python3')
 has_mako = run_command(
   prog_python, '-c',
   '''
-from distutils.version import StrictVersion
+try:
+  from packaging.version import Version
+except:
+  from distutils.version import StrictVersion as Version
 import mako
-assert StrictVersion(mako.__version__) >= StrictVersion("0.8.0")
+assert Version(mako.__version__) >= Version("0.8.0")
   ''', check: false)
 if has_mako.returncode() != 0
   error('Python (3.x) mako module >= 0.8.0 required to build mesa.')

src/amd/ci/radv-navi10-aco-fails.txt

@@ -1,3 +1,2 @@
 # New CTS failures in 1.3.7.0
 dEQP-VK.api.version_check.unavailable_entry_points,Fail
-dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail

src/amd/ci/radv-polaris10-aco-fails.txt

@@ -20,4 +20,3 @@ dEQP-VK.texture.mipmap.cubemap.image_view_min_lod.base_level.nearest_nearest,Fai
 
 # New CTS failures in 1.3.7.0.
 dEQP-VK.api.version_check.unavailable_entry_points,Fail
-dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail

src/amd/ci/radv-renoir-aco-fails.txt

@@ -1,3 +1,2 @@
 # New CTS failures in 1.3.7.0.
 dEQP-VK.api.version_check.unavailable_entry_points,Fail
-dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.partial_binding_depth_stencil,Fail

src/amd/common/ac_rgp.c

@@ -79,9 +79,9 @@ struct sqtt_file_chunk_header {
 struct sqtt_file_header_flags {
    union {
       struct {
-         int32_t is_semaphore_queue_timing_etw : 1;
-         int32_t no_queue_semaphore_timestamps : 1;
-         int32_t reserved : 30;
+         uint32_t is_semaphore_queue_timing_etw : 1;
+         uint32_t no_queue_semaphore_timestamps : 1;
+         uint32_t reserved : 30;
       };
 
       uint32_t value;

src/amd/compiler/aco_optimizer.cpp

@@ -1440,15 +1440,15 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
             instr->operands[i].setTemp(info.temp);
          } else if (info.is_neg() && can_use_mod && mod_bitsize_compat &&
                     can_eliminate_fcanonicalize(ctx, instr, info.temp, i)) {
-            if (!instr->isDPP() && !instr->isSDWA())
+            if (!instr->isDPP16() && can_use_VOP3(ctx, instr))
                instr->format = asVOP3(instr->format);
             instr->operands[i].setTemp(info.temp);
             if (!instr->valu().abs[i])
                instr->valu().neg[i] = true;
          }
          if (info.is_abs() && can_use_mod && mod_bitsize_compat &&
              can_eliminate_fcanonicalize(ctx, instr, info.temp, i)) {
-            if (!instr->isDPP() && !instr->isSDWA())
+            if (!instr->isDPP16() && can_use_VOP3(ctx, instr))
                instr->format = asVOP3(instr->format);
             instr->operands[i] = Operand(info.temp);
             instr->valu().abs[i] = true;

src/amd/compiler/tests/glsl_scraper.py

@@ -28,16 +28,16 @@ def __init__(self, *args):
 }
 
 base_layout_qualifier_id_re = r'({0}\s*=\s*(?P<{0}>\d+))'
-id_re = '(?P<name_%d>[^(gl_)]\w+)'
-type_re = '(?P<dtype_%d>\w+)'
+id_re = r'(?P<name_%d>[^(gl_)]\w+)'
+type_re = r'(?P<dtype_%d>\w+)'
 location_re = base_layout_qualifier_id_re.format('location')
 component_re = base_layout_qualifier_id_re.format('component')
 binding_re = base_layout_qualifier_id_re.format('binding')
 set_re = base_layout_qualifier_id_re.format('set')
 unk_re = r'\w+(=\d+)?'
 layout_qualifier_re = r'layout\W*\((%s)+\)' % '|'.join([location_re, binding_re, set_re, unk_re, '[, ]+'])
-ubo_decl_re = 'uniform\W+%s(\W*{)?(?P<type_ubo>)' % (id_re%0)
-ssbo_decl_re = 'buffer\W+%s(\W*{)?(?P<type_ssbo>)' % (id_re%1)
+ubo_decl_re = r'uniform\W+%s(\W*{)?(?P<type_ubo>)' % (id_re%0)
+ssbo_decl_re = r'buffer\W+%s(\W*{)?(?P<type_ssbo>)' % (id_re%1)
 image_buffer_decl_re = r'uniform\W+imageBuffer\w+%s;(?P<type_img_buf>)' % (id_re%2)
 image_decl_re = r'uniform\W+image\w+\W+%s;(?P<type_img>)' % (id_re%3)
 texture_buffer_decl_re = r'uniform\W+textureBuffer\w+%s;(?P<type_tex_buf>)' % (id_re%4)

src/amd/vulkan/radv_cmd_buffer.c

@@ -2271,17 +2271,19 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
 static void
 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer)
 {
+   const struct radv_rendering_state *render = &cmd_buffer->state.render;
    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
+   const bool stencil_test_enable =
+      d->vk.ds.stencil.test_enable && (render->ds_att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
 
-   radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
-                          S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) |
-                             S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) |
-                             S_028800_ZFUNC(d->vk.ds.depth.compare_op) |
-                             S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) |
-                             S_028800_STENCIL_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) |
-                             S_028800_BACKFACE_ENABLE(d->vk.ds.stencil.test_enable ? 1 : 0) |
-                             S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) |
-                             S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare));
+   radeon_set_context_reg(
+      cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL,
+      S_028800_Z_ENABLE(d->vk.ds.depth.test_enable ? 1 : 0) |
+         S_028800_Z_WRITE_ENABLE(d->vk.ds.depth.write_enable ? 1 : 0) | S_028800_ZFUNC(d->vk.ds.depth.compare_op) |
+         S_028800_DEPTH_BOUNDS_ENABLE(d->vk.ds.depth.bounds_test.enable ? 1 : 0) |
+         S_028800_STENCIL_ENABLE(stencil_test_enable) | S_028800_BACKFACE_ENABLE(stencil_test_enable) |
+         S_028800_STENCILFUNC(d->vk.ds.stencil.front.op.compare) |
+         S_028800_STENCILFUNC_BF(d->vk.ds.stencil.back.op.compare));
 }
 
 static void
@@ -5861,6 +5863,11 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi
             render->ds_att.format = inheritance_info->depthAttachmentFormat;
          if (inheritance_info->stencilAttachmentFormat != VK_FORMAT_UNDEFINED)
             render->ds_att.format = inheritance_info->stencilAttachmentFormat;
+
+         if (vk_format_has_depth(render->ds_att.format))
+            render->ds_att_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
+         if (vk_format_has_stencil(render->ds_att.format))
+            render->ds_att_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
       }
 
       cmd_buffer->state.inherited_pipeline_statistics = pBeginInfo->pInheritanceInfo->pipelineStatistics;
@@ -7716,6 +7723,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
    }
 
    struct radv_attachment ds_att = {.iview = NULL};
+   VkImageAspectFlags ds_att_aspects = 0;
    const VkRenderingAttachmentInfo *d_att_info = pRenderingInfo->pDepthAttachment;
    const VkRenderingAttachmentInfo *s_att_info = pRenderingInfo->pStencilAttachment;
    if ((d_att_info != NULL && d_att_info->imageView != VK_NULL_HANDLE) ||
@@ -7751,7 +7759,16 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
 
       assert(d_iview == NULL || s_iview == NULL || d_iview == s_iview);
       ds_att.iview = d_iview ? d_iview : s_iview, ds_att.format = ds_att.iview->vk.format;
-      radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview);
+
+      if (d_iview && s_iview) {
+         ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT;
+      } else if (d_iview) {
+         ds_att_aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
+      } else {
+         ds_att_aspects = VK_IMAGE_ASPECT_STENCIL_BIT;
+      }
+
+      radv_initialise_ds_surface(cmd_buffer->device, &ds_att.ds, ds_att.iview, ds_att_aspects);
 
       assert(d_res_iview == NULL || s_res_iview == NULL || d_res_iview == s_res_iview);
       ds_att.resolve_iview = d_res_iview ? d_res_iview : s_res_iview;
@@ -7800,14 +7817,15 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
    render->color_att_count = pRenderingInfo->colorAttachmentCount;
    typed_memcpy(render->color_att, color_att, render->color_att_count);
    render->ds_att = ds_att;
+   render->ds_att_aspects = ds_att_aspects;
    render->vrs_att = vrs_att;
    render->vrs_texel_size = vrs_texel_size;
    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
 
    if (cmd_buffer->device->physical_device->rad_info.rbplus_allowed)
       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
 
-   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
+   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | RADV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE;
 
    if (render->vrs_att.iview && cmd_buffer->device->physical_device->rad_info.gfx_level == GFX10_3) {
       if (render->ds_att.iview) {
@@ -10592,7 +10610,10 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_inf
    }
 
    radv_gang_barrier(cmd_buffer, 0, dst_stage_mask);
-   radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask);
+
+   const bool is_gfx_or_ace = cmd_buffer->qf == RADV_QUEUE_GENERAL || cmd_buffer->qf == RADV_QUEUE_COMPUTE;
+   if (is_gfx_or_ace)
+      radv_cp_dma_wait_for_stages(cmd_buffer, src_stage_mask);
 
    cmd_buffer->state.flush_bits |= dst_flush_bits;
 

src/amd/vulkan/radv_device.c

@@ -1842,7 +1842,7 @@ radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_
 
 void
 radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
-                           struct radv_image_view *iview)
+                           struct radv_image_view *iview, VkImageAspectFlags ds_aspects)
 {
    unsigned level = iview->vk.base_mip_level;
    unsigned format, stencil_format;
@@ -1859,7 +1859,9 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
    stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
 
    uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
-   ds->db_depth_view = S_028008_SLICE_START(iview->vk.base_array_layer) | S_028008_SLICE_MAX(max_slice);
+   ds->db_depth_view = S_028008_SLICE_START(iview->vk.base_array_layer) | S_028008_SLICE_MAX(max_slice) |
+                       S_028008_Z_READ_ONLY(!(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) |
+                       S_028008_STENCIL_READ_ONLY(!(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT));
    if (device->physical_device->rad_info.gfx_level >= GFX10) {
       ds->db_depth_view |=
          S_028008_SLICE_START_HI(iview->vk.base_array_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11);

src/amd/vulkan/radv_pipeline_rt.c

@@ -609,6 +609,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca
    radv_shader_layout_init(pipeline_layout, MESA_SHADER_INTERSECTION, &traversal_stage.layout);
    result = radv_rt_nir_to_asm(device, cache, pCreateInfo, key, pipeline, false, &traversal_stage, NULL, NULL,
                                &pipeline->base.base.shaders[MESA_SHADER_INTERSECTION]);
+   ralloc_free(traversal_module.nir);
 
 cleanup:
    for (uint32_t i = 0; i < pCreateInfo->stageCount; i++)