Skip to content

Commit

Permalink
minor update
Browse files Browse the repository at this point in the history
  • Loading branch information
tinebp committed Oct 17, 2024
1 parent 91fee5d commit 6b1091e
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 3 deletions.
4 changes: 3 additions & 1 deletion hw/rtl/cache/VX_cache_bank.sv
Original file line number Diff line number Diff line change
Expand Up @@ -616,7 +616,9 @@ module VX_cache_bank #(
.ready_out (core_rsp_ready)
);

assign crsp_queue_stall = crsp_queue_valid && ~crsp_queue_ready;
// we use 'do_read_st1' instead 'crsp_queue_valid'
// to remove costly 'is_hit_st1' signal from critical paths.
assign crsp_queue_stall = do_read_st1 && ~crsp_queue_ready;

// schedule memory request

Expand Down
4 changes: 2 additions & 2 deletions hw/rtl/cache/VX_cache_mshr.sv
Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,8 @@ module VX_cache_mshr #(
);
`UNUSED_PARAM (BANK_ID)

reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
reg [MSHR_ADDR_WIDTH-1:0] next_index [MSHR_SIZE-1:0];
reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [0:MSHR_SIZE-1];
reg [MSHR_ADDR_WIDTH-1:0] next_index [0:MSHR_SIZE-1];

reg [MSHR_SIZE-1:0] valid_table, valid_table_n;
reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n;
Expand Down

0 comments on commit 6b1091e

Please sign in to comment.