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viktor-prutyanov / drec-fpga-intro Public

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Viktor Prutyanov edited this page Mar 17, 2019 · 8 revisions

Toggle table of contents Pages 18

Home
Icarus Verilog and GTKWave
Problem 00: Invertor
Problem 01: Sign extension block
Problem 02: Clock divider
Problem 03: Blinking LED
Problem 04: Hex display
Problem 05: Hex counter
Problem 06: ROM
Problem 07: CPU v1
Problem 08: CPU v2
Problem 09: CPU v3
Problem 10: PLL
Problem 11: UART MMIO
Quartus 18.1
RISC V toolchain
USB Blaster
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