some config change

ucb-bar · Sep 24, 2024 · d2c6c8f · d2c6c8f
1 parent 03c9449
commit d2c6c8f
Showing 1 changed file with 19 additions and 16 deletions.
diff --git a/src/main/scala/gemmini/Configs.scala b/src/main/scala/gemmini/Configs.scala
@@ -162,8 +162,8 @@ object GemminiConfigs {
     ex_write_to_spad = true,
     ex_write_to_acc = true,
 
-    use_tl_spad_mem = true,
-    tl_spad_mem_base = 0x1000000,
+    //use_tl_spad_mem = true,
+    //tl_spad_mem_base = 0x1000000,
   )
 
   val dummyConfig = GemminiArrayConfig[DummySInt, Float, Float](
@@ -240,6 +240,8 @@ object GemminiConfigs {
 
   val leanConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true)
 
+  val PGAsConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true, use_tl_spad_mem = true, tl_spad_mem_base = 0x1000000)
+
   val leanPrintfConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true, use_firesim_simulation_counters=true)
 
 }
@@ -261,23 +263,27 @@ class DefaultGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
   )
 })
 
-/**
- * Mixin which sets the default lean parameters for a systolic array accelerator.
- */
-class LeanGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
-  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanConfig
+
+class GemminiPGAsConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
+  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.PGAsConfig,
+  tl_spad_mem_base: BigInt = 0
 ) extends Config((site, here, up) => {
   case BuildRoCC => up(BuildRoCC) ++ Seq(
     (p: Parameters) => {
       implicit val q = p
-      val gemmini = LazyModule(new Gemmini(gemminiConfig))
+      val gemmini = LazyModule(new Gemmini(gemminiConfig.copy(
+        tl_spad_mem_base = tl_spad_mem_base
+      )))
       gemmini
     }
   )
 })
 
-class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
-  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanPrintfConfig
+/**
+ * Mixin which sets the default lean parameters for a systolic array accelerator.
+ */
+class LeanGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
+  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanConfig
 ) extends Config((site, here, up) => {
   case BuildRoCC => up(BuildRoCC) ++ Seq(
     (p: Parameters) => {
@@ -288,16 +294,13 @@ class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
   )
 })
 
-class LeanGemminiPGASConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
-  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanConfig,
-  tl_spad_mem_base: BigInt = 0
+class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
+  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanPrintfConfig
 ) extends Config((site, here, up) => {
   case BuildRoCC => up(BuildRoCC) ++ Seq(
     (p: Parameters) => {
       implicit val q = p
-      val gemmini = LazyModule(new Gemmini(gemminiConfig.copy(
-        tl_spad_mem_base = tl_spad_mem_base
-      )))
+      val gemmini = LazyModule(new Gemmini(gemminiConfig))
       gemmini
     }
   )