initial attempt for gemv

src/main/scala/gemmini/Configs.scala

@@ -29,14 +29,14 @@ object GemminiConfigs {
     tileRows = 1,
     tileColumns = 1,
     meshRows = 16,
-    meshColumns = 16,
+    meshColumns = 1,
 
     // Spatial array PE options
-    dataflow = Dataflow.BOTH,
+    dataflow = Dataflow.WS,
 
     // Scratchpad and accumulator
-    sp_capacity = CapacityInKilobytes(256),
-    acc_capacity = CapacityInKilobytes(64),
+    sp_capacity = CapacityInKilobytes(64),
+    acc_capacity = CapacityInKilobytes(32),
 
     sp_banks = 4,
     acc_banks = 2,
@@ -45,9 +45,10 @@ object GemminiConfigs {
     acc_singleported = false,
 
     // DNN options
-    has_training_convs = true,
-    has_max_pool = true,
+    has_training_convs = false,
+    has_max_pool = false,
     has_nonlinear_activations = true,
+    has_first_layer_optimizations = false,
 
     // Reservation station entries
     reservation_station_entries_ld = 8,
@@ -151,15 +152,15 @@ object GemminiConfigs {
     )),
 
     // SoC counters options
-    num_counter = 8,
+    num_counter = 0,
 
     // Scratchpad and Accumulator input/output options
-    acc_read_full_width = true,
+    acc_read_full_width = false,
     acc_read_small_width = true,
 
     ex_read_from_spad = true,
-    ex_read_from_acc = true,
-    ex_write_to_spad = true,
+    ex_read_from_acc = false,
+    ex_write_to_spad = false,
     ex_write_to_acc = true,
   )
 

src/main/scala/gemmini/Controller.scala

@@ -54,7 +54,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   ext_mem_io.foreach(_ <> outer.spad.module.io.ext_mem.get)
 
   val tagWidth = 32
-
+/*
   // Counters
   val counters = Module(new CounterController(outer.config.num_counter, outer.xLen))
   io.resp <> counters.io.out  // Counter access command will be committed immediately
@@ -63,7 +63,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   counters.io.in.valid := false.B
   counters.io.in.bits := DontCare
   counters.io.event_io.collect(spad.module.io.counter)
-
+*/
   // TLB
   implicit val edge = outer.spad.id_node.edges.out.head
   val tlb = Module(new FrontendTLB(2, tlb_size, dma_maxbytes, use_tlb_register_filter, use_firesim_simulation_counters, use_shared_tlb))
@@ -74,7 +74,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
 
   io.ptw <> tlb.io.ptw
 
-  counters.io.event_io.collect(tlb.io.counter)
+  //counters.io.event_io.collect(tlb.io.counter)
 
   spad.module.io.flush := tlb.io.exp.map(_.flush()).reduce(_ || _)
 
@@ -122,7 +122,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   */
 
   val reservation_station = withClock (gated_clock) { Module(new ReservationStation(outer.config, new GemminiCmd(reservation_station_entries))) }
-  counters.io.event_io.collect(reservation_station.io.counter)
+  //counters.io.event_io.collect(reservation_station.io.counter)
 
   when (io.cmd.valid && io.cmd.bits.inst.funct === CLKGATE_EN && !io.busy) {
     clock_en_reg := io.cmd.bits.rs1(0)
@@ -161,7 +161,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
 
   val unrolled_cmd = Queue(loop_cmd)
   unrolled_cmd.ready := false.B
-  counters.io.event_io.connectEventSignal(CounterEvent.LOOP_MATMUL_ACTIVE_CYCLES, loop_matmul_unroller_busy)
+  //counters.io.event_io.connectEventSignal(CounterEvent.LOOP_MATMUL_ACTIVE_CYCLES, loop_matmul_unroller_busy)
 
   // Wire up controllers to ROB
   reservation_station.io.alloc.valid := false.B
@@ -189,9 +189,9 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   val store_controller = withClock (gated_clock) { Module(new StoreController(outer.config, coreMaxAddrBits, local_addr_t)) }
   val ex_controller = withClock (gated_clock) { Module(new ExecuteController(xLen, tagWidth, outer.config)) }
 
-  counters.io.event_io.collect(load_controller.io.counter)
-  counters.io.event_io.collect(store_controller.io.counter)
-  counters.io.event_io.collect(ex_controller.io.counter)
+  //counters.io.event_io.collect(load_controller.io.counter)
+  //counters.io.event_io.collect(store_controller.io.counter)
+  //counters.io.event_io.collect(ex_controller.io.counter)
 
   /*
   tiler.io.issue.load.ready := false.B
@@ -254,33 +254,20 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   ex_controller.io.acc.read_resp <> spad.module.io.acc.read_resp
   ex_controller.io.acc.write <> spad.module.io.acc.write
 
-  // Im2Col unit
-  val im2col = withClock (gated_clock) { Module(new Im2Col(outer.config)) }
-
-  // Wire up Im2col
-  counters.io.event_io.collect(im2col.io.counter)
-  // im2col.io.sram_reads <> spad.module.io.srams.read
-  im2col.io.req <> ex_controller.io.im2col.req
-  ex_controller.io.im2col.resp <> im2col.io.resp
-
-  // Wire arbiter for ExecuteController and Im2Col scratchpad reads
-  (ex_controller.io.srams.read, im2col.io.sram_reads, spad.module.io.srams.read).zipped.foreach { case (ex_read, im2col_read, spad_read) =>
-    val req_arb = Module(new Arbiter(new ScratchpadReadReq(n=sp_bank_entries), 2))
+  (ex_controller.io.srams.read, spad.module.io.srams.read).zipped.foreach { case (ex_read, spad_read) =>
+    val req_arb = Module(new Arbiter(new ScratchpadReadReq(n=sp_bank_entries), 1))
 
     req_arb.io.in(0) <> ex_read.req
-    req_arb.io.in(1) <> im2col_read.req
 
     spad_read.req <> req_arb.io.out
 
     // TODO if necessary, change how the responses are handled when fromIm2Col is added to spad read interface
 
     ex_read.resp.valid := spad_read.resp.valid
-    im2col_read.resp.valid := spad_read.resp.valid
 
     ex_read.resp.bits := spad_read.resp.bits
-    im2col_read.resp.bits := spad_read.resp.bits
 
-    spad_read.resp.ready := ex_read.resp.ready || im2col_read.resp.ready
+    spad_read.resp.ready := ex_read.resp.ready 
   }
 
   // Wire up controllers to ROB
@@ -343,15 +330,15 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   val incr_st_ex_cycles = !load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy
 
   val incr_ld_st_ex_cycles = load_controller.io.busy && store_controller.io.busy && ex_controller.io.busy
-
+/*
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_CYCLES, incr_ld_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_CYCLES, incr_st_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_EX_CYCLES, incr_ex_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_CYCLES, incr_ld_st_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_EX_CYCLES, incr_ld_ex_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_ST_EX_CYCLES, incr_st_ex_cycles)
   counters.io.event_io.connectEventSignal(CounterEvent.MAIN_LD_ST_EX_CYCLES, incr_ld_st_ex_cycles)
-
+*/
   // Issue commands to controllers
   // TODO we combinationally couple cmd.ready and cmd.valid signals here
   // when (compressed_cmd.valid) {
@@ -382,9 +369,9 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
 
     .elsewhen (is_counter_op) {
       // If this is a counter access/configuration command, execute immediately
-      counters.io.in.valid := unrolled_cmd.valid
-      unrolled_cmd.ready := counters.io.in.ready
-      counters.io.in.bits := unrolled_cmd.bits.cmd
+      //counters.io.in.valid := unrolled_cmd.valid
+      //unrolled_cmd.ready := counters.io.in.ready
+      //counters.io.in.bits := unrolled_cmd.bits.cmd
     }
 
     .elsewhen (is_clock_gate_en) {

src/main/scala/gemmini/DMA.scala

@@ -67,7 +67,7 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
       val busy = Output(Bool())
       val flush = Input(Bool())
 
-      val counter = new CounterEventIO()
+      //val counter = new CounterEventIO()
     })
 
     val nCmds = (nXacts / meshRows) + 1
@@ -108,8 +108,8 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
     io.resp.bits.bytes_read := RegEnable(xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
     io.resp.bits.last := beatPacker.io.out.bits.last
 
-    io.counter.collect(core.module.io.counter)
-    io.counter.collect(xactTracker.io.counter)
+    //io.counter.collect(core.module.io.counter)
+    //io.counter.collect(xactTracker.io.counter)
   }
 }
 
@@ -150,7 +150,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
       val beatData = Decoupled(new StreamReadBeat(nXacts, beatBits, maxBytes))
       val tlb = new FrontendTLBIO
       val flush = Input(Bool())
-      val counter = new CounterEventIO()
+      //val counter = new CounterEventIO()
     })
 
     val s_idle :: s_req_new_block :: Nil = Enum(2)
@@ -303,7 +303,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
 
       state := s_req_new_block
     }
-
+/*
     // Performance counter
     CounterEventIO.init(io.counter)
     io.counter.connectEventSignal(CounterEvent.RDMA_ACTIVE_CYCLE, state =/= s_idle)
@@ -330,7 +330,9 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
         printf(SynthesizePrintf("RDMA bytes rec: %d\n", total_bytes_read))
       }
     }
+    */
   }
+
 }
 
 class StreamWriteRequest(val dataWidth: Int, val maxBytes: Int)(implicit p: Parameters) extends CoreBundle {
@@ -606,7 +608,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
       assert(io.req.bits.len <= (block_cols * inputType.getWidth / 8).U || io.req.bits.block === 0.U, "DMA can't write multiple blocks to main memory when writing full accumulator output")
       assert(!io.req.bits.pool_en || io.req.bits.block === 0.U, "Can't pool with block-mvout")
     }
-
+/*
     // Performance counter
     CounterEventIO.init(io.counter)
     io.counter.connectEventSignal(CounterEvent.WDMA_ACTIVE_CYCLE, state =/= s_idle)
@@ -641,5 +643,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
         printf(SynthesizePrintf("WDMA total latency: %d\n", total_latency))
       }
     }
+    */
   }
+
 }