fixing int compile issues

ucb-bar · Jul 26, 2024 · d1463c6 · d1463c6
1 parent 3bad911
commit d1463c6
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/src/main/scala/gemmini/Configs.scala b/src/main/scala/gemmini/Configs.scala
@@ -33,7 +33,7 @@ object GemminiConfigs {
     tileColumns = 1,
     meshRows = 16,
     meshColumns = 16,
-    quantWidth = 4,
+    quantWidth = 2,
 
     // Spatial array PE options
     dataflow = Dataflow.BOTH,
@@ -165,6 +165,8 @@ object GemminiConfigs {
     ex_read_from_acc = true,
     ex_write_to_spad = true,
     ex_write_to_acc = true,
+    use_tl_spad_mem = true,
+    tl_spad_mem_base = 0x1000000
   )
 
   val dummyConfig = GemminiArrayConfig[DummySInt, Float, Float](
@@ -247,7 +249,7 @@ object GemminiConfigs {
 
   val leanPrintfConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true, use_firesim_simulation_counters=true)
 
-  val lutLeanConfig = defaultConfig.copy(dataflow=Dataflow.WS, inputType=SInt(16.W), meshRows=8, meshColumns=8, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true)
+  val lutLeanConfig = defaultConfig.copy(dataflow=Dataflow.WS, inputType=SInt(8.W), meshRows=8, meshColumns=8, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true)
 
 }