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Fix missing connections with DontCares
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jerryz123 committed Aug 20, 2023
1 parent ff55883 commit 94250b2
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Showing 3 changed files with 8 additions and 2 deletions.
4 changes: 4 additions & 0 deletions src/main/scala/gemmini/DMA.scala
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,7 @@ class StreamReader[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T
io.resp.bits.bytes_read := RegEnable(xactTracker.io.peek.entry.bytes_to_read, beatPacker.io.req.fire)
io.resp.bits.last := beatPacker.io.out.bits.last

io.counter := DontCare
io.counter.collect(core.module.io.counter)
io.counter.collect(xactTracker.io.counter)
}
Expand Down Expand Up @@ -231,6 +232,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
tlb_q.io.enq <> tlb_arb.io.out

io.tlb.req.valid := tlb_q.io.deq.valid
io.tlb.req.bits := DontCare
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
io.tlb.req.bits.tlb_req.passthrough := false.B
io.tlb.req.bits.tlb_req.size := 0.U // send_size
Expand Down Expand Up @@ -305,6 +307,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf
}

// Performance counter
io.counter := DontCare
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.RDMA_ACTIVE_CYCLE, state =/= s_idle)
io.counter.connectEventSignal(CounterEvent.RDMA_TLB_WAIT_CYCLES, io.tlb.resp.miss)
Expand Down Expand Up @@ -522,6 +525,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes:
tlb_q.io.enq <> tlb_arb.io.out

io.tlb.req.valid := tlb_q.io.deq.fire
io.tlb.req.bits := DontCare
io.tlb.req.bits.tlb_req.vaddr := tlb_q.io.deq.bits.vaddr
io.tlb.req.bits.tlb_req.passthrough := false.B
io.tlb.req.bits.tlb_req.size := 0.U // send_size
Expand Down
5 changes: 3 additions & 2 deletions src/main/scala/gemmini/FrontendTLB.scala
Original file line number Diff line number Diff line change
Expand Up @@ -30,15 +30,15 @@ class DecoupledTLB(entries: Int, maxSize: Int, use_firesim_simulation_counters:
extends CoreModule {

val lgMaxSize = log2Ceil(maxSize)
val io = new Bundle {
val io = IO(new Bundle {
val req = Flipped(Valid(new DecoupledTLBReq(lgMaxSize)))
val resp = new TLBResp
val ptw = new TLBPTWIO

val exp = new TLBExceptionIO

val counter = new CounterEventIO()
}
})

val interrupt = RegInit(false.B)
io.exp.interrupt := interrupt
Expand Down Expand Up @@ -156,6 +156,7 @@ class FrontendTLB(nClients: Int, entries: Int, maxSize: Int, use_tlb_register_fi

// TODO Return the sum of the TLB counters, rather than just the counters of the first TLB. This only matters if we're
// not using the shared TLB
io.counter := DontCare
tlbs.foreach(_.io.counter.external_reset := false.B)
io.counter.collect(tlbs.head.io.counter)
}
1 change: 1 addition & 0 deletions src/main/scala/gemmini/Scratchpad.scala
Original file line number Diff line number Diff line change
Expand Up @@ -825,6 +825,7 @@ class Scratchpad[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T,
}

// Counter connection
io.counter := DontCare
io.counter.collect(reader.module.io.counter)
io.counter.collect(writer.module.io.counter)
}
Expand Down

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