An agile package manager and extensible build tool for HDLs
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Updated
Jul 9, 2024 - Rust
An agile package manager and extensible build tool for HDLs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Sol-1: A CPU/Computer System made from 74 series logic.
A web-based IDE for https://nand2tetris.org
HDL libraries and projects
A go-to repository for exploring, learning, and mastering RTL design and verification.
Test suite designed to check compliance with the SystemVerilog standard.
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
A toolbox for automating some of the more tedious refactoring tasks comming with common HDL languages (VHDL/Verilog). Including among others: entity to instance conversion and entity cross language conversion.
A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.
A modern hardware definition language and toolchain based on Python
Playground for VGA projects on Tiny Tapeout
A 32-bit CPU being developed in SpinalHDL
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