gtkwave
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Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
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Dec 22, 2023 - Verilog
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Jan 9, 2021 - SystemVerilog
Implementación del procesador monociclo RISC-V en System Verilog.
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May 6, 2024 - SystemVerilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
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Mar 22, 2024 - Verilog
This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.
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Jun 16, 2018 - Verilog
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
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Jul 8, 2022 - Verilog
Practice Codes of Verilog Language
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Apr 1, 2024 - Verilog
Course Project - Advanced Computer Architecture - Autumn Semester 2022 - Indian Institute of Technology Bombay
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Dec 13, 2022 - VHDL
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
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Jul 3, 2024 - Verilog
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
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Jul 9, 2024
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