MIPS32 Pipeline Processor

Introduction

This repository contains the Verilog implementation of a MIPS32 pipeline processor. The design is based on the book "Digital Design and Computer Architecture" by David Money Harris and Sarah L. Harris. The processor includes a 5-stage pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB), along with a hazard detection unit to manage data and control hazards.

Implementation

Stages

1. Instruction Fetch (IF): Fetches the instruction from the instruction memory.
2. Instruction Decode (ID): Decodes the fetched instruction and reads the necessary registers.
3. Execute (EX): Performs arithmetic or logical operations.
4. Memory Access (MEM): Accesses data memory for load and store instructions.
5. Write Back (WB): Writes the result back to the register file.

Instruction Set

The MIPS32 pipeline processor currently supports the following instructions:

• add - Add
• sub - Subtract
• or - Bitwise OR
• and - Bitwise AND
• slt - Set Less Than
• addi - Add Immediate
• lw - Load Word
• sw - Store Word
• beq - Branch if Equal
• j - Jump

Hazard Unit

The hazard unit is responsible for detecting and resolving data and control hazards. It ensures that the pipeline operates smoothly without conflicts. The unit implements forwarding and stalling mechanisms to handle different types of hazards.

Datapath

Tools

• Verilog compiler (such as Icarus Verilog)
• Simulator (such as Modelsim)

References

Digital Design and Computer Architecture by David Money Harris & Sarah L. Harris