Fix the problem of cache handling with DMA.

Issue #156
Cache handling API should not call when the D Cache is disabled.

CHANGELOG.md

@@ -31,6 +31,7 @@ Record of the modification in project development.
 - [Issue 153 : STM32H5 target has warning of the implicit declaration. ](https://github.com/suikan4github/murasaki/issues/153)
 - [Issue 154 : Template for STM32L152 has wrong UART_PORT define. ](https://github.com/suikan4github/murasaki/issues/154)
 - [Issue 155 : I2C legacy API of CubeHAL causes compile error on STM32H5 ](https://github.com/suikan4github/murasaki/issues/155)
+- [Issue 156 : Cache handling API should not call when the D Cache is disabled. ](https://github.com/suikan4github/murasaki/issues/156)
 
 ### Security
 ### Known Issue

core/murasaki_defs.hpp

@@ -342,15 +342,19 @@ static inline bool IsInsideInterrupt()
 static inline void CleanAndInvalidateDataCacheByAddress(void *address, size_t size)
                                                         {
 #ifdef __CORE_CM7_H_GENERIC
-    unsigned int aligned_address = reinterpret_cast<unsigned int>(address);
-
-    // extract modulo 32. The address have to be aligned to 32byte.
-    unsigned int adjustment = aligned_address & 0x1F;
-    // Adjust the address and size.
-    aligned_address -= adjustment;  // aligne to 32byte boarder
-    size += adjustment;  // Because the start address is lower, the size is bigger.
-
-    ::SCB_CleanInvalidateDCache_by_Addr(reinterpret_cast<long unsigned int *>(aligned_address), size);
+	// Is data cache enabled? then, invalidate it
+	if (( SCB->CCR & SCB_CCR_DC_Msk ) != 0 )
+	{
+		unsigned int aligned_address = reinterpret_cast<unsigned int>(address);
+
+		// extract modulo 32. The address have to be aligned to 32byte.
+		unsigned int adjustment = aligned_address & 0x1F;
+		// Adjust the address and size.
+		aligned_address -= adjustment;  // aligne to 32byte boarder
+		size += adjustment;  // Because the start address is lower, the size is bigger.
+
+		::SCB_CleanInvalidateDCache_by_Addr(reinterpret_cast<long unsigned int *>(aligned_address), size);
+	}
 #elif defined ( __CORE_CM0_H_GENERIC ) ||defined ( __CORE_CM0PLUS_H_GENERIC ) ||defined ( __CORE_CM3_H_GENERIC ) ||defined ( __CORE_CM4_H_GENERIC ) ||defined ( __CORE_CM1_H_GENERIC )  ||defined ( __CORE_CM33_H_GENERIC )
 // Do nothing. These core doesn't have d-cache.
 #else
@@ -373,15 +377,19 @@ static inline void CleanAndInvalidateDataCacheByAddress(void *address, size_t si
 static inline void CleanDataCacheByAddress(void *address, size_t size)
                                            {
 #ifdef __CORE_CM7_H_GENERIC
-    unsigned int aligned_address = reinterpret_cast<unsigned int>(address);
-
-    // extract modulo 32. The address have to be aligned to 32byte.
-    unsigned int adjustment = aligned_address & 0x1F;
-    // Adjust the address and size.
-    aligned_address -= adjustment;  // aligne to 32byte boarder
-    size += adjustment;  // Because the start address is lower, the size is bigger.
-
-    ::SCB_CleanDCache_by_Addr(reinterpret_cast<long unsigned int *>(aligned_address), size);
+	// Is data cache enabled? then, clean the data cache
+	if (( SCB->CCR & SCB_CCR_DC_Msk ) != 0 )
+	{
+		unsigned int aligned_address = reinterpret_cast<unsigned int>(address);
+
+		// extract modulo 32. The address have to be aligned to 32byte.
+		unsigned int adjustment = aligned_address & 0x1F;
+		// Adjust the address and size.
+		aligned_address -= adjustment;  // aligne to 32byte boarder
+		size += adjustment;  // Because the start address is lower, the size is bigger.
+
+		::SCB_CleanDCache_by_Addr(reinterpret_cast<long unsigned int *>(aligned_address), size);
+	}
 #elif defined ( __CORE_CM0_H_GENERIC ) ||defined ( __CORE_CM0PLUS_H_GENERIC ) ||defined ( __CORE_CM3_H_GENERIC ) ||defined ( __CORE_CM4_H_GENERIC ) ||defined ( __CORE_CM1_H_GENERIC ) ||defined ( __CORE_CM33_H_GENERIC )
 // Do nothing. These core doesn't have d-cache.
 #else

drivers/pll/si5351.cpp

@@ -320,6 +320,8 @@ Si5351Status Si5351::SetFrequency(murasaki::Si5351Pll pll, unsigned int div_ch,
 
     // Reset the PLL to make phase offset correct. This is required by specification.
     ResetPLL(pll);
+
+    return ( Si5351Status::ks5351Ok);
 }
 
 Si5351Status Si5351::SetQuadratureFrequency(murasaki::Si5351Pll pll, unsigned int divI_ch, unsigned int divQ_ch, uint32_t frequency) {
@@ -421,6 +423,8 @@ Si5351Status Si5351::SetQuadratureFrequency(murasaki::Si5351Pll pll, unsigned in
 
     // Reset the PLL to make phase offset correct. This is required by specification.
     ResetPLL(pll);
+
+    return( Si5351Status::ks5351Ok);
 }
 
 //@formatter:off