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Protocol
Although creating a parallel EEPROM programmer was the original intent of the project, the same protocol should work equally well for other memory programming devices. This page serves as documentation for future implementations.
A conforming USB device should be implemented using the vendor specific class. At a minimum, the device should provide two bulk transfer endpoints (EP 1 IN/OUT) on Interface 0 for protocol-level communication. The maximum packet size for EP 1 OUT should be sized according to the largest supported page size. EP 1 IN sizing is less critical, however larger sizes will yield better read performance. It is suggested that the same value be used for both endpoints.
The github.com/sstallion/go-eeprom package can be considered a reference implementation for interacting with a conforming device.
Every operation begins with a command (OUT) packet, which consists of a single byte that indicates the command followed by zero or more bytes that serve as parameters. All multi-byte parameters are interpreted as little-endian by the device.
Command packets should contain at most one command; additional payload will be discarded by the device.
A Read is indicated by 0x52 ('R'). Two parameters are required: the starting address and length of data to be transferred expressed as N-1. Both parameters are 16-bit unsigned integers. The device will respond with one or more data (IN) packets containing the data.
A Byte Write is indicated by 0x57 ('W'). Two parameters are required: the starting address and length of data to be transferred expressed as N-1. Both parameters are 16-bit unsigned integers. One or more data (OUT) packets should follow containing the data.
A Page Write is indicated by 0x50 ('P'). Two parameters are required: the starting address and length of data to be transferred expressed as N-1. Both parameters are 16-bit unsigned integers. One or more data (OUT) packets should follow containing the data. Data packets should be sized according to the page size, not to exceed the maximum packet size of the endpoint.
A Chip Erase is indicated by 0x5A ('Z').
Upon completion of a command, the device will respond with a status (IN) packet that contains a 16-bit unsigned integer. For data transfer commands this will be the next address to read or write. For a chip erase, this will always be zero.
A device reset may be issued to abort the current command. Resets should be issued following a failed transfer to clear device state.