Merge pull request #1115 from slaclab/idelaye3Fix

fix idelaye3 issues - busy signal and placement
slaclab · Sep 27, 2023 · aeef7c7 · aeef7c7
2 parents ec5cb1b + f36227b
commit aeef7c7
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd
@@ -134,7 +134,7 @@ begin
          -- Outputs
          patchLoad     <= r.Load;
          patchCntValue <= r.dlyValue;
-         if (v.dlyTarget /= CNTVALUEOUT) or (r.state /= IDLE_S) then
+         if (r.state /= IDLE_S) then
             busy <= '1';
          else
             busy <= '0';

diff --git a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd
@@ -37,7 +37,8 @@ entity Idelaye3Wrapper is
       IS_RST_INVERTED  : bit     := '0';  -- Optional inversion for RST
       REFCLK_FREQUENCY : real    := 300.0;  -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
       SIM_DEVICE       : string  := "ULTRASCALE";  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS)
-      UPDATE_MODE      : string  := "ASYNC");  -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
+      UPDATE_MODE      : string  := "ASYNC";
+      IODELAY_GROUP_G  : string  := "DLYGRP_C");  -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
    port (
       BUSY        : out sl;             -- 1-bit output: Patch module is busy
       CASC_OUT    : out sl;  -- 1-bit output: Cascade delay output to ODELAY input cascade
@@ -62,6 +63,9 @@ architecture rtl of Idelaye3Wrapper is
    signal patchCntValue   : slv(8 downto 0);
    signal patchLoad       : sl;
 
+   attribute IODELAY_GROUP            : string;
+   attribute IODELAY_GROUP of U_IDELAYE3 : label is IODELAY_GROUP_G;
+
 begin
 
    CNTVALUEOUT <= currentCntValue;