migrating RoCEv2 src code from FilMarini:surf:roce

ethernet/EthMacCore/blue-crc/BluespecFifo2.v

@@ -0,0 +1,153 @@
+// Copied from https://github.com/B-Lang-org/bsc/blob/2024.07/src/Verilog/FIFO2.v
+`ifdef BSV_ASSIGNMENT_DELAY
+`else
+  `define BSV_ASSIGNMENT_DELAY
+`endif
+
+`ifdef BSV_POSITIVE_RESET
+  `define BSV_RESET_VALUE 1'b1
+  `define BSV_RESET_EDGE posedge
+`else
+  `define BSV_RESET_VALUE 1'b0
+  `define BSV_RESET_EDGE negedge
+`endif
+
+`ifdef BSV_ASYNC_RESET
+ `define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
+`else
+ `define BSV_ARESET_EDGE_META
+`endif
+
+`ifdef BSV_RESET_FIFO_HEAD
+ `define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
+`else
+ `define BSV_ARESET_EDGE_HEAD
+`endif
+
+// Depth 2 FIFO
+module BluespecFifo2(CLK,
+             RST,
+             D_IN,
+             ENQ,
+             FULL_N,
+             D_OUT,
+             DEQ,
+             EMPTY_N,
+             CLR);
+
+   parameter width = 1;
+   parameter guarded = 1'b1;
+
+   input     CLK ;
+   input     RST ;
+   input [width - 1 : 0] D_IN;
+   input                 ENQ;
+   input                 DEQ;
+   input                 CLR ;
+
+   output                FULL_N;
+   output                EMPTY_N;
+   output [width - 1 : 0] D_OUT;
+
+   reg                    full_reg;
+   reg                    empty_reg;
+   reg [width - 1 : 0]    data0_reg;
+   reg [width - 1 : 0]    data1_reg;
+
+   assign                 FULL_N = full_reg ;
+   assign                 EMPTY_N = empty_reg ;
+   assign                 D_OUT = data0_reg ;
+
+
+   // Optimize the loading logic since state encoding is not power of 2!
+   wire                   d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
+   wire                   d0d1 = DEQ && ! full_reg ;
+   wire                   d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
+   wire                   d1di = ENQ & empty_reg ;
+
+`ifdef BSV_NO_INITIAL_BLOCKS
+`else // not BSV_NO_INITIAL_BLOCKS
+   // synopsys translate_off
+   initial
+     begin
+        data0_reg   = {((width + 1)/2) {2'b10}} ;
+        data1_reg  = {((width + 1)/2) {2'b10}} ;
+        empty_reg = 1'b0;
+        full_reg  = 1'b1;
+     end // initial begin
+   // synopsys translate_on
+`endif // BSV_NO_INITIAL_BLOCKS
+
+   always@(posedge CLK `BSV_ARESET_EDGE_META)
+     begin
+        if (RST == `BSV_RESET_VALUE)
+          begin
+             empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
+             full_reg  <= `BSV_ASSIGNMENT_DELAY 1'b1;
+          end // if (RST == `BSV_RESET_VALUE)
+        else
+          begin
+             if (CLR)
+               begin
+                  empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
+                  full_reg  <= `BSV_ASSIGNMENT_DELAY 1'b1;
+               end // if (CLR)
+             else if ( ENQ && ! DEQ ) // just enq
+               begin
+                  empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
+                  full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
+               end
+             else if ( DEQ && ! ENQ )
+               begin
+                  full_reg  <= `BSV_ASSIGNMENT_DELAY 1'b1;
+                  empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
+               end // if ( DEQ && ! ENQ )
+          end // else: !if(RST == `BSV_RESET_VALUE)
+
+     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
+
+
+   always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
+     begin
+`ifdef BSV_RESET_FIFO_HEAD
+        if (RST == `BSV_RESET_VALUE)
+          begin
+             data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
+             data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
+          end
+        else
+`endif
+          begin
+             data0_reg  <= `BSV_ASSIGNMENT_DELAY
+                           {width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
+             data1_reg <= `BSV_ASSIGNMENT_DELAY
+                          d1di ? D_IN : data1_reg ;
+          end // else: !if(RST == `BSV_RESET_VALUE)
+     end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
+
+
+
+   // synopsys translate_off
+   always@(posedge CLK)
+     begin: error_checks
+        reg deqerror, enqerror ;
+
+        deqerror =  0;
+        enqerror = 0;
+        if (RST == ! `BSV_RESET_VALUE)
+          begin
+             if ( ! empty_reg && DEQ )
+               begin
+                  deqerror =  1;
+                  $display( "Warning: BluespecFifo2: %m -- Dequeuing from empty fifo" ) ;
+               end
+             if ( ! full_reg && ENQ && (!DEQ || guarded) )
+               begin
+                  enqerror = 1;
+                  $display( "Warning: BluespecFifo2: %m -- Enqueuing to a full fifo" ) ;
+               end
+          end
+     end // always@ (posedge CLK)
+   // synopsys translate_on
+
+endmodule

ethernet/EthMacCore/blue-crc/EthMacCrcAxiStreamWrapperRecv.vhd

@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: Wrapper on mkCrcRawAxiStreamCustomRecv.v
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiStreamPkg.all;
+
+entity EthMacCrcAxiStreamWrapperRecv is
+   generic (
+      TPD_G : time := 1 ns);
+   port (
+      -- Clock and Reset
+      ethClk      : in  sl;
+      ethRst      : in  sl;
+      -- Slave ports
+      sAxisMaster : in  AxiStreamMasterType;
+      sAxisSlave  : out AxiStreamSlaveType;
+      -- Master ports
+      mAxisMaster : out AxiStreamMasterType;
+      mAxisSlave  : in  AxiStreamSlaveType);
+end EthMacCrcAxiStreamWrapperRecv;
+
+architecture rtl of EthMacCrcAxiStreamWrapperRecv is
+
+   component mkCrcRawAxiStreamCustomRecv is
+      port (
+         CLK                : in  std_logic;
+         RST_N              : in  std_logic;
+         s_axis_tvalid      : in  std_logic;
+         s_axis_tdata       : in  std_logic_vector(255 downto 0);
+         s_axis_tkeep       : in  std_logic_vector(31 downto 0);
+         s_axis_tlast       : in  std_logic;
+         s_axis_tuser       : in  std_logic;
+         s_axis_tready      : out std_logic;
+         m_crc_stream_data  : out std_logic_vector(31 downto 0);
+         m_crc_stream_valid : out std_logic;
+         m_crc_stream_ready : in  std_logic);
+   end component mkCrcRawAxiStreamCustomRecv;
+
+   -- BlueRdma
+   signal blueRstN         : sl;
+   signal bluetValidSlave  : sl;
+   signal bluetDataSlave   : slv(255 downto 0);
+   signal bluetKeepSlave   : slv(31 downto 0);
+   signal bluetUserSlave   : sl;
+   signal bluetLastSlave   : sl;
+   signal bluetReadySlave  : sl;
+   signal bluetDataMaster  : slv(31 downto 0);
+   signal bluetValidMaster : sl;
+   signal bluetReadyMaster : sl;
+
+begin
+
+   blueRstN <= not ethRst;
+
+   -----------------------------------------------------------------------------
+   -- IP integrator
+   -----------------------------------------------------------------------------
+   MasterAxiStreamIpIntegrator_1 : entity surf.MasterAxiStreamIpIntegrator
+      generic map (
+         TUSER_WIDTH     => 1,
+         TDATA_NUM_BYTES => 32)
+      port map (
+         M_AXIS_ACLK     => ethClk,
+         M_AXIS_ARESETN  => blueRstN,
+         M_AXIS_TVALID   => bluetValidSlave,
+         M_AXIS_TDATA    => bluetDataSlave,
+         M_AXIS_TKEEP    => bluetKeepSlave,
+         M_AXIS_TLAST    => bluetLastSlave,
+         M_AXIS_TUSER(0) => bluetUserSlave,
+         M_AXIS_TREADY   => bluetReadySlave,
+         axisClk         => open,
+         axisRst         => open,
+         axisMaster      => sAxisMaster,
+         axisSlave       => sAxisSlave);
+
+   SlaveAxiStreamIpIntegrator_1 : entity surf.SlaveAxiStreamIpIntegrator
+      generic map (
+         HAS_TLAST       => 1,
+         HAS_TKEEP       => 1,
+         TDATA_NUM_BYTES => 4)
+      port map (
+         S_AXIS_ACLK    => ethClk,
+         S_AXIS_ARESETN => blueRstN,
+         S_AXIS_TVALID  => bluetValidMaster,
+         S_AXIS_TDATA   => bluetDataMaster,
+         S_AXIS_TKEEP   => x"F",
+         S_AXIS_TLAST   => '1',
+         S_AXIS_TREADY  => bluetReadyMaster,
+         axisClk        => open,
+         axisRst        => open,
+         axisMaster     => mAxisMaster,
+         axisSlave      => mAxisSlave);
+
+   -----------------------------------------------------------------------------
+   -- CRC calculator
+   -----------------------------------------------------------------------------
+   mkCrcRawAxiStreamCustomRecv_1 : mkCrcRawAxiStreamCustomRecv
+      port map (
+         CLK                => ethClk,
+         RST_N              => blueRstN,
+         s_axis_tvalid      => bluetValidSlave,
+         s_axis_tdata       => bluetDataSlave,
+         s_axis_tkeep       => bluetKeepSlave,
+         s_axis_tlast       => bluetLastSlave,
+         s_axis_tuser       => bluetUserSlave,
+         s_axis_tready      => bluetReadySlave,
+         m_crc_stream_data  => bluetDataMaster,
+         m_crc_stream_valid => bluetValidMaster,
+         m_crc_stream_ready => bluetReadyMaster);
+
+end rtl;