cherry picking the surf AxiStreamFifoV2 changes up to v2.5.0

... but comment out the RST_ASYNC_G related changes
slaclab · Sep 20, 2024 · 6c978b9 · 6c978b9
1 parent b40b1e3
commit 6c978b9
Showing 1 changed file with 14 additions and 7 deletions.
diff --git a/axi/axi-stream/rtl/AxiStreamFifoV2.vhd b/axi/axi-stream/rtl/AxiStreamFifoV2.vhd
@@ -28,7 +28,7 @@ entity AxiStreamFifoV2 is
    generic (
       -- General Configurations
       TPD_G             : time                  := 1 ns;
-      RST_ASYNC_G       : boolean               := false;
+--      RST_ASYNC_G       : boolean               := false;
       INT_PIPE_STAGES_G : natural range 0 to 16 := 0;  -- Internal FIFO setting
       PIPE_STAGES_G     : natural range 0 to 16 := 1;
       SLAVE_READY_EN_G  : boolean               := true;
@@ -90,6 +90,8 @@ end AxiStreamFifoV2;
 
 architecture rtl of AxiStreamFifoV2 is
 
+   constant RST_ASYNC_G : boolean := false; -- workaround for this cherry picked code for SMURF
+
    constant LAST_FIFO_ADDR_WIDTH_C : integer range 4 to 48 :=
       ite(LAST_FIFO_ADDR_WIDTH_G < 4, FIFO_ADDR_WIDTH_G, LAST_FIFO_ADDR_WIDTH_G);
 
@@ -185,7 +187,7 @@ begin
    U_SlaveResize : entity surf.AxiStreamGearbox
       generic map (
          TPD_G               => TPD_G,
-         RST_ASYNC_G         => RST_ASYNC_G,
+--         RST_ASYNC_G         => RST_ASYNC_G,
          READY_EN_G          => SLAVE_READY_EN_G,
          SLAVE_AXI_CONFIG_G  => SLAVE_AXI_CONFIG_G,
          MASTER_AXI_CONFIG_G => FIFO_CONFIG_C)
@@ -240,7 +242,7 @@ begin
          LAST_STAGE_ASYNC_G => true,
          PIPE_STAGES_G      => INT_PIPE_STAGES_G,
          RST_POLARITY_G     => '1',
-         RST_ASYNC_G        => false, -- Synchronous reset might be required here
+--         RST_ASYNC_G        => false, -- Synchronous reset might be required here
          GEN_SYNC_FIFO_G    => GEN_SYNC_FIFO_G,
          FWFT_EN_G          => true,
          SYNTH_MODE_G       => SYNTH_MODE_G,
@@ -277,7 +279,7 @@ begin
             LAST_STAGE_ASYNC_G => true,
             PIPE_STAGES_G      => INT_PIPE_STAGES_G,
             RST_POLARITY_G     => '1',
-            RST_ASYNC_G        => false, -- Synchronous reset might be required here
+--            RST_ASYNC_G        => false, -- Synchronous reset might be required here
             GEN_SYNC_FIFO_G    => GEN_SYNC_FIFO_G,
             MEMORY_TYPE_G      => "distributed",
             FWFT_EN_G          => true,
@@ -313,7 +315,12 @@ begin
                -- Start output when a block or end of frame is available
                elsif fifoValidLast = '1' or (VALID_THOLD_G /= 0 and fifoRdCount >= VALID_THOLD_G) then
                   fifoInFrame <= '1' after TPD_G;
+
+               -- Prevent the FIFO from locking up when frame deeper than what the U_Fifo can hold
+               elsif (fifoAFull = '1') then
+                  fifoInFrame <= '1' after TPD_G;
                end if;
+
             end if;
          end process;
 
@@ -387,7 +394,7 @@ begin
    U_MasterResize : entity surf.AxiStreamGearbox
       generic map (
          TPD_G               => TPD_G,
-         RST_ASYNC_G         => RST_ASYNC_G,
+--         RST_ASYNC_G         => RST_ASYNC_G,
          READY_EN_G          => true,
          SIDE_BAND_WIDTH_G   => 8,
          SLAVE_AXI_CONFIG_G  => FIFO_CONFIG_C,
@@ -410,7 +417,7 @@ begin
    Synchronizer_1 : entity surf.Synchronizer
       generic map (
          TPD_G          => TPD_G,
-         RST_ASYNC_G    => RST_ASYNC_G,
+--         RST_ASYNC_G    => RST_ASYNC_G,
          OUT_POLARITY_G => '0')         -- invert
       port map (
          clk     => sAxisClk,
@@ -425,7 +432,7 @@ begin
    U_Pipe : entity surf.AxiStreamPipeline
       generic map (
          TPD_G             => TPD_G,
-         RST_ASYNC_G       => RST_ASYNC_G,
+--         RST_ASYNC_G       => RST_ASYNC_G,
          SIDE_BAND_WIDTH_G => 8,
          PIPE_STAGES_G     => PIPE_STAGES_G)
       port map (