adding ROCEV2_EN_G generic to Ethernet lib

slaclab · Sep 19, 2024 · 6635803 · 6635803
1 parent a86edfd
commit 6635803
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Showing 38 changed files with 132 additions and 45 deletions.
diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd
@@ -31,6 +31,7 @@ entity EthMacRx is
       PHY_TYPE_G     : string           := "XGMII";
       JUMBO_G        : boolean          := true;
       -- Misc. Configurations
+      ROCEV2_EN_G    : boolean          := false;
       FILT_EN_G      : boolean          := false;
       BYP_EN_G       : boolean          := false;
       BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000";
@@ -131,8 +132,9 @@ begin
    ---------------------
    U_Csum : entity surf.EthMacRxCsum
       generic map (
-         TPD_G   => TPD_G,
-         JUMBO_G => JUMBO_G)
+         TPD_G       => TPD_G,
+         JUMBO_G     => JUMBO_G,
+         ROCEV2_EN_G => ROCEV2_EN_G)
       port map (
          -- Clock and Reset
          ethClk      => ethClk,
@@ -148,17 +150,23 @@ begin
    --------------------------------
    -- RoCEv2 Protocol iCRC Checking
    --------------------------------
-   U_RoCEv2 : entity surf.EthMacRxRoCEv2
-      generic map (
-         TPD_G => TPD_G)
-      port map (
-         -- Clock and Reset
-         ethClk         => ethClk,
-         ethRst         => ethRst,
-         -- Checksum Interface
-         obCsumMaster   => obCsumMaster,
-         -- Bypass Interface
-         ibBypassMaster => ibBypassMaster);
+   GEN_RoCEv2 : if (ROCEV2_EN_G = true) generate
+      U_RoCEv2 : entity surf.EthMacRxRoCEv2
+         generic map (
+            TPD_G => TPD_G)
+         port map (
+            -- Clock and Reset
+            ethClk         => ethClk,
+            ethRst         => ethRst,
+            -- Checksum Interface
+            obCsumMaster   => obCsumMaster,
+            -- Bypass Interface
+            ibBypassMaster => ibBypassMaster);
+   end generate;
+
+   BYPASS_RoCEv2 : if (ROCEV2_EN_G = false) generate
+      ibBypassMaster <= obCsumMaster;
+   end generate;
 
    -------------------
    -- RX Bypass Module

diff --git a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd
@@ -25,8 +25,9 @@ use surf.EthMacPkg.all;
 
 entity EthMacRxCsum is
    generic (
-      TPD_G   : time    := 1 ns;
-      JUMBO_G : boolean := true);
+      TPD_G       : time    := 1 ns;
+      JUMBO_G     : boolean := true;
+      ROCEV2_EN_G : boolean := false);
    port (
       -- Clock and Reset
       ethClk      : in  sl;
@@ -283,7 +284,7 @@ begin
                   v.protLen(0)(15 downto 8)  := sAxisMaster.tData(55 downto 48);
                   v.protLen(0)(7 downto 0)   := sAxisMaster.tData(63 downto 56);
                end if;
-               if sAxisMaster.tData(47 downto 32) = x"B712" then
+               if ROCEV2_EN_G and (sAxisMaster.tData(47 downto 32) = x"B712") then
                   v.roce(0) := '1';
                else
                   v.roce(0) := '0';
@@ -356,6 +357,11 @@ begin
          axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v.mAxisMasters(EMAC_CSUM_PIPELINE_C+1), EMAC_FRAG_BIT_C, r.fragDet(EMAC_CSUM_PIPELINE_C), 0);
       end if;
 
+      -- Outputs
+      mAxisMaster          <= r.mAxisMasters(EMAC_CSUM_PIPELINE_C+1);
+      mAxisMaster.tDest(0) <= r.roce(EMAC_CSUM_PIPELINE_C);
+      dbg                  <= dummy;
+
       -- Reset
       if (ethRst = '1') then
          v := REG_INIT_C;
@@ -364,11 +370,6 @@ begin
       -- Register the variable for next clock cycle
       rin <= v;
 
-      -- Outputs
-      mAxisMaster          <= r.mAxisMasters(EMAC_CSUM_PIPELINE_C+1);
-      mAxisMaster.tDest(0) <= r.roce(EMAC_CSUM_PIPELINE_C);
-      dbg                  <= dummy;
-
    end process comb;
 
    seq : process (ethClk) is

diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd
@@ -39,6 +39,7 @@ entity EthMacTop is
       SYNTH_MODE_G      : string                   := "inferred";
       MEMORY_TYPE_G     : string                   := "block";
       -- Misc. Configurations
+      ROCEV2_EN_G       : boolean                  := false;
       FILT_EN_G         : boolean                  := false;
       PRIM_COMMON_CLK_G : boolean                  := false;
       PRIM_CONFIG_G     : AxiStreamConfigType      := EMAC_AXIS_CONFIG_C;
@@ -159,6 +160,7 @@ begin
          DROP_ERR_PKT_G  => DROP_ERR_PKT_G,
          JUMBO_G         => JUMBO_G,
          -- Misc. Configurations
+         ROCEV2_EN_G     => ROCEV2_EN_G,
          BYP_EN_G        => BYP_EN_G,
          -- RAM sythesis Mode
          SYNTH_MODE_G    => SYNTH_MODE_G)
@@ -224,6 +226,7 @@ begin
          PHY_TYPE_G     => PHY_TYPE_G,
          JUMBO_G        => JUMBO_G,
          -- Misc. Configurations
+         ROCEV2_EN_G    => ROCEV2_EN_G,
          FILT_EN_G      => FILT_EN_G,
          BYP_EN_G       => BYP_EN_G,
          BYP_ETH_TYPE_G => BYP_ETH_TYPE_G,

diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd
@@ -33,6 +33,7 @@ entity EthMacTx is
       DROP_ERR_PKT_G  : boolean                  := true;
       JUMBO_G         : boolean                  := true;
       -- Misc. Configurations
+      ROCEV2_EN_G     : boolean                  := false;
       BYP_EN_G        : boolean                  := false;
       -- RAM Synthesis mode
       SYNTH_MODE_G    : string                   := "inferred");
@@ -114,7 +115,9 @@ begin
       generic map (
          TPD_G          => TPD_G,
          DROP_ERR_PKT_G => DROP_ERR_PKT_G,
-         JUMBO_G        => JUMBO_G)
+         JUMBO_G        => JUMBO_G,
+         ROCEV2_EN_G    => ROCEV2_EN_G,
+         SYNTH_MODE_G   => SYNTH_MODE_G)
       port map (
          -- Clock and Reset
          ethClk      => ethClk,
@@ -132,19 +135,26 @@ begin
    ---------------------------------
    -- RoCEv2 Protocol iCRC insertion
    ---------------------------------
-   U_RoCEv2 : entity surf.EthMacTxRoCEv2
-      generic map (
-         TPD_G => TPD_G)
-      port map (
-         -- Clock and Reset
-         ethClk        => ethClk,
-         ethRst        => ethRst,
-         -- Checksum Interface
-         obCsumMaster  => obCsumMaster,
-         obCsumSlave   => obCsumSlave,
-         -- Pause Interface
-         ibPauseMaster => ibPauseMaster,
-         ibPauseSlave  => ibPauseSlave);
+   GEN_RoCEv2 : if (ROCEV2_EN_G = true) generate
+      U_RoCEv2 : entity surf.EthMacTxRoCEv2
+         generic map (
+            TPD_G => TPD_G)
+         port map (
+            -- Clock and Reset
+            ethClk        => ethClk,
+            ethRst        => ethRst,
+            -- Checksum Interface
+            obCsumMaster  => obCsumMaster,
+            obCsumSlave   => obCsumSlave,
+            -- Pause Interface
+            ibPauseMaster => ibPauseMaster,
+            ibPauseSlave  => ibPauseSlave);
+   end generate;
+
+   BYPASS_RoCEv2 : if (ROCEV2_EN_G = false) generate
+      ibPauseMaster <= obCsumMaster;
+      obCsumSlave   <= ibPauseSlave;
+   end generate;
 
    ------------------
    -- TX Pause Module

diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd
@@ -28,6 +28,7 @@ entity EthMacTxCsum is
       TPD_G          : time    := 1 ns;
       DROP_ERR_PKT_G : boolean := true;
       JUMBO_G        : boolean := true;
+      ROCEV2_EN_G    : boolean := false;
       SYNTH_MODE_G   : string  := "inferred");  -- Synthesis mode for internal RAMs
    port (
       -- Clock and Reset
@@ -335,7 +336,7 @@ begin
                   v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0);
                end if;
                -- Track the number of bytes and check if its a RoCE transmission (UDP dst port = 4791)
-               if rxMaster.tData(47 downto 32) = x"B712" then
+               if ROCEV2_EN_G and (rxMaster.tData(47 downto 32) = x"B712") then
                   v.roce(0)    := '1';
                   v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2 + ROCEV2_CRC32_BYTE_WIDTH_C;
                   v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2 + ROCEV2_CRC32_BYTE_WIDTH_C;
@@ -425,7 +426,7 @@ begin
             v.mSlave.tReady := '1';
             -- Move data
             v.txMaster      := mMaster;
-            if roce = '1' then
+            if ROCEV2_EN_G and (roce = '1') then
                v.txMaster.tDest(0) := '1';
             else
                v.txMaster.tDest(0) := '0';
@@ -468,7 +469,7 @@ begin
                   -- Overwrite the data field
                   v.txMaster.tData(55 downto 48) := protLen(15 downto 8);
                   v.txMaster.tData(63 downto 56) := protLen(7 downto 0);
-                  if roce = '1' then
+                  if ROCEV2_EN_G and (roce = '1') then
                      v.txMaster.tData(71 downto 64) := (others => '0');
                      v.txMaster.tData(79 downto 72) := (others => '0');
                   else
@@ -514,9 +515,11 @@ begin
          end if;
       end if;
 
-      -- Combinatorial outputs before the reset
-      rxSlave <= v.rxSlave;
-      mSlave  <= v.mSlave;
+      -- Outputs
+      sMaster  <= r.sMaster;
+      txMaster <= r.txMaster;
+      rxSlave  <= v.rxSlave;
+      mSlave   <= v.mSlave;
 
       -- Reset
       if (ethRst = '1') then
@@ -526,10 +529,6 @@ begin
       -- Register the variable for next clock cycle
       rin <= v;
 
-      -- Registered Outputs
-      sMaster  <= r.sMaster;
-      txMaster <= r.txMaster;
-
    end process comb;
 
    seq : process (ethClk) is

diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd
@@ -28,6 +28,7 @@ entity GigEthGth7 is
       TPD_G           : time                := 1 ns;
       JUMBO_G         : boolean             := true;
       PAUSE_EN_G      : boolean             := true;
+      ROCEV2_EN_G     : boolean             := false;
       -- AXI-Lite Configurations
       EN_AXI_REG_G    : boolean             := false;
       -- AXI Streaming Configurations
@@ -174,6 +175,7 @@ begin
          JUMBO_G         => JUMBO_G,
          PAUSE_EN_G      => PAUSE_EN_G,
          PAUSE_512BITS_G => PAUSE_512BITS_C,
+         ROCEV2_EN_G     => ROCEV2_EN_G,
          PHY_TYPE_G      => "GMII",
          PRIM_CONFIG_G   => AXIS_CONFIG_G)
       port map (

diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd
@@ -33,6 +33,7 @@ entity GigEthGth7Wrapper is
       NUM_LANE_G         : natural range 1 to 4             := 1;
       JUMBO_G            : boolean                          := true;
       PAUSE_EN_G         : boolean                          := true;
+      ROCEV2_EN_G         : boolean                         := false;
       -- Clocking Configurations
       USE_GTREFCLK_G     : boolean                          := false;  --  FALSE: gtClkP/N,  TRUE: gtRefClk
       CLKIN_PERIOD_G     : real                             := 8.0;
@@ -169,6 +170,7 @@ begin
             TPD_G           => TPD_G,
             JUMBO_G         => JUMBO_G,
             PAUSE_EN_G      => PAUSE_EN_G,
+            ROCEV2_EN_G     => ROCEV2_EN_G,
             -- AXI-Lite Configurations
             EN_AXI_REG_G    => EN_AXI_REG_G,
             -- AXI Streaming Configurations

diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd
@@ -33,6 +33,7 @@ entity GigEthGthUltraScale is
       MEMORY_TYPE_G     : string              := "ultra";
       JUMBO_G           : boolean             := true;
       PAUSE_EN_G        : boolean             := true;
+      ROCEV2_EN_G       : boolean             := false;
       -- AXI-Lite Configurations
       EN_AXI_REG_G      : boolean             := false;
       -- AXI Streaming Configurations
@@ -188,6 +189,7 @@ begin
          JUMBO_G           => JUMBO_G,
          PAUSE_EN_G        => PAUSE_EN_G,
          PAUSE_512BITS_G   => PAUSE_512BITS_C,
+         ROCEV2_EN_G       => ROCEV2_EN_G,
          PHY_TYPE_G        => "GMII",
          PRIM_CONFIG_G     => AXIS_CONFIG_G)
       port map (

diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd
@@ -39,6 +39,7 @@ entity GigEthGthUltraScaleWrapper is
       MEMORY_TYPE_G      : string                           := "ultra";
       JUMBO_G            : boolean                          := true;
       PAUSE_EN_G         : boolean                          := true;
+      ROCEV2_EN_G        : boolean                          := false;
       -- Clocking Configurations
       EXT_PLL_G          : boolean                          := false;
       USE_GTREFCLK_G     : boolean                          := false;  --  FALSE: gtClkP/N,  TRUE: gtRefClk
@@ -208,6 +209,7 @@ begin
             MEMORY_TYPE_G     => MEMORY_TYPE_G,
             JUMBO_G           => JUMBO_G,
             PAUSE_EN_G        => PAUSE_EN_G,
+            ROCEV2_EN_G       => ROCEV2_EN_G,
             -- AXI-Lite Configurations
             EN_AXI_REG_G      => EN_AXI_REG_G,
             -- AXI Streaming Configurations

diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd
@@ -28,6 +28,7 @@ entity GigEthGthUltraScale is
       TPD_G           : time                := 1 ns;
       JUMBO_G         : boolean             := true;
       PAUSE_EN_G      : boolean             := true;
+      ROCEV2_EN_G     : boolean             := false;
       -- AXI-Lite Configurations
       EN_AXI_REG_G    : boolean             := false;
       -- AXI Streaming Configurations
@@ -186,6 +187,7 @@ begin
          JUMBO_G         => JUMBO_G,
          PAUSE_EN_G      => PAUSE_EN_G,
          PAUSE_512BITS_G => PAUSE_512BITS_C,
+         ROCEV2_EN_G     => ROCEV2_EN_G,
          PHY_TYPE_G      => "GMII",
          PRIM_CONFIG_G   => AXIS_CONFIG_G)
       port map (

diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd
@@ -33,6 +33,7 @@ entity GigEthGthUltraScaleWrapper is
       NUM_LANE_G         : natural range 1 to 4             := 1;
       JUMBO_G            : boolean                          := true;
       PAUSE_EN_G         : boolean                          := true;
+      ROCEV2_EN_G        : boolean                          := false;
       -- Clocking Configurations
       EXT_PLL_G          : boolean                          := false;
       USE_GTREFCLK_G     : boolean                          := false;  --  FALSE: gtClkP/N,  TRUE: gtRefClk
@@ -196,6 +197,7 @@ begin
             TPD_G         => TPD_G,
             JUMBO_G       => JUMBO_G,
             PAUSE_EN_G    => PAUSE_EN_G,
+            ROCEV2_EN_G   => ROCEV2_EN_G,
             -- AXI-Lite Configurations
             EN_AXI_REG_G  => EN_AXI_REG_G,
             -- AXI Streaming Configurations

diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd
@@ -28,6 +28,7 @@ entity GigEthGtp7 is
       TPD_G           : time                := 1 ns;
       JUMBO_G         : boolean             := true;
       PAUSE_EN_G      : boolean             := true;
+      ROCEV2_EN_G     : boolean             := false;
       -- AXI-Lite Configurations
       EN_AXI_REG_G    : boolean             := false;
       -- AXI Streaming Configurations
@@ -228,6 +229,7 @@ begin
          JUMBO_G         => JUMBO_G,
          PAUSE_EN_G      => PAUSE_EN_G,
          PAUSE_512BITS_G => PAUSE_512BITS_C,
+         ROCEV2_EN_G     => ROCEV2_EN_G,
          PHY_TYPE_G      => "GMII",
          PRIM_CONFIG_G   => AXIS_CONFIG_G)
       port map (

diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd
@@ -33,6 +33,7 @@ entity GigEthGtp7Wrapper is
       NUM_LANE_G         : natural range 1 to 4 := 1;
       JUMBO_G            : boolean              := true;
       PAUSE_EN_G         : boolean              := true;
+      ROCEV2_EN_G        : boolean              := false;
       -- Clocking Configurations
       USE_GTREFCLK_G     : boolean              := false;
       --  FALSE: gtClkP/N,  TRUE: gtRefClk
@@ -224,6 +225,7 @@ begin
                TPD_G           => TPD_G,
                JUMBO_G         => JUMBO_G,
                PAUSE_EN_G      => PAUSE_EN_G,
+               ROCEV2_EN_G     => ROCEV2_EN_G,
                -- AXI-Lite Configurations
                EN_AXI_REG_G    => EN_AXI_REG_G,
                -- AXI Streaming Configurations

diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd
@@ -29,6 +29,7 @@ entity GigEthGtx7 is
       TPD_G                   : time                := 1 ns;
       JUMBO_G                 : boolean             := true;
       PAUSE_EN_G              : boolean             := true;
+      ROCEV2_EN_G             : boolean             := false;
       SYNTH_MODE_G            : string              := "inferred";
       -- AXI-Lite Configurations
       EN_AXI_REG_G            : boolean             := false;
@@ -239,6 +240,7 @@ begin
          JUMBO_G         => JUMBO_G,
          PAUSE_EN_G      => PAUSE_EN_G,
          PAUSE_512BITS_G => PAUSE_512BITS_C,
+         ROCEV2_EN_G     => ROCEV2_EN_G,
          PHY_TYPE_G      => "GMII",
          SYNTH_MODE_G    => SYNTH_MODE_G,
          PRIM_CONFIG_G   => AXIS_CONFIG_G)