Merge pull request #651 from martinbarez/patch-1

Tang nano 20k: Fix clock pin number
sipeed · Apr 7, 2024 · 512038e · 512038e
2 parents 9457be3 + 0336866
commit 512038e
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/docs/hardware/en/tang/tang-nano-20k/example/unbox.md b/docs/hardware/en/tang/tang-nano-20k/example/unbox.md
@@ -73,7 +73,7 @@ MS5351 can generate 3 clock output, we can see its clock output pin via the sche
 
 ![unbox_uart_bl616_ms351_clk_pin](./../../../../zh/tang/tang-nano-20k/assets/unbox/unbox_uart_bl616_ms351_clk_pin.png)
 
-The CLK0 clock is connected with the PIN10 of FPGA, and CLK1 clock is connected with the PIN14 of FPGA, CLK2 clock is connected with the PIN13 of FPGA.
+The CLK0 clock is connected with the PIN10 of FPGA, and CLK1 clock is connected with the PIN11 of FPGA, CLK2 clock is connected with the PIN13 of FPGA.
 
 - Set CLK1 output 50M clock
 
@@ -238,4 +238,4 @@ Power on Tang Nano 20K, we can see the game menu. The number of games and the na
 
 ## FPGA Development guide
 
-[Blink the LED](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/led.html)
+[Blink the LED](https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/example/led.html)