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licheervnano: doc update
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@Zepan
Zepan authored Apr 28, 2024
2 parents cb83841 + 1d5af5b commit 06792f0
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249 changes: 249 additions & 0 deletions docs/hardware/zh/lichee/RV_Nano/5_peripheral.md
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Expand Up @@ -65,6 +65,12 @@ echo userspace > /dev/console
echo kernel > /dev/kmsg
```

另一种方法是在/boot/uEnv.txt中加入以下内容将console换到别的tty上:

```
consoledev=/dev/ttyX
```

### UART1 UART2 UART3

UART1和2的引脚默认用作连接UART蓝牙芯片:
Expand All @@ -77,6 +83,8 @@ mmio_write_32(0x03001068, 0x4); // GPIOA 18 UART1 CTS
mmio_write_32(0x03001064, 0x4); // GPIOA 19 UART1 RTS
```

如果只想使用UART1，则不需要更改PINMUX，只需要连接 GPIOA28 GPIOA29

如果想要同时使用UART1和UART2的功能，则需要写入寄存器来设置引脚的PINMUX:

在Linux用户空间可以使用devmem工具来写入寄存器
Expand Down Expand Up @@ -620,3 +628,244 @@ echo 1 | evtest
```

然后按下USER按键，可以在终端看到对应的事件报告


## JTAG

需要下载平头哥的调试服务器:

https://xuantie.t-head.cn/community/download?id=4209675990638596096

如何安装:

https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1682234034575/T-Head+Debugger+Server+User+Guide+%28ZH-CN%29.pdf

准备一个Slogic Combo 8，切换到CKLINK模式，并连接到JTAG引脚:

如何连接:

https://wiki.sipeed.com/hardware/zh/logic_analyzer/combo8/use_cklink_function.html

RV Nano的JTAG引脚:

```
PA19 JTAG_TMS
PA18 JTAG_TCK
PA29 JTAG_TDO
PA28 JTAG_TDI
```

然后将调试器连接到电脑，切换到CKLINK模式，给板子上电，按住RESET按钮，然后松开的时候启动DebugServer:


下面是启动成功的输出:

```
user@lu:~$ DebugServerConsole --debug connect -setclk 10K
+--- ---+
| T-Head Debugger Server (Build: Aug 3 2023, Linux) |
User Layer Version : 5.16.11
Target Layer version : 2.0
| Copyright (C) 2023 T-HEAD Semiconductor Co.,Ltd. |
+--- ---+
CONNECT: Start to connect target (Enter target_open).
CONNECT: Detect JTAG port for RISC-V cores.
CONNECT: Configure cJTAG with 2-wires
CONNECT: Configure CDI type to 2-wires.
CONNECT: Read IDCODE Gets 0x0, Invalid IDCODE.
CONNECT: Configure CDI type to 5-wires.
CONNECT: Read IDCODE Gets 0x10000b6f, Manufid is 0x5b7.
CONNECT: T-HEAD with ManufactueID 0x5b7 is found, Debug Arch maybe RISCV DM.
CONNECT: JTAG Port: JTAG-5
CONNECT: Check the DEBUG ARCH automatically.
CONNECT: Read IDCODE Gets 0x10000b6f, Manufid is 0x5b7.
CONNECT: T-HEAD with ManufactueID 0x5b7 is found, Debug Arch maybe RISCV DM.
CONNECT: Try to connect target and get arch_ops.
T-HEAD: CKLink_Lite_V2, App_ver unknown, Bit_ver null, Clock 10.010KHz,
5-wire, With DDC, Cache Flush On, SN CKLink_Lite_Vendor-FactoryAIOT.
CONNECT: +--Attempt to connect Debug Transport Module.--+
CONNECT: Read IDCODE.
CONNECT: Read DTM IDCODE get 0x10000b6f, it is T-HEAD implementation.
CONNECT: Check whether DMIACC is supported.
CONNECT: DMIACC is supported.
CONNECT: Read DTM Debug Control and Status.
CONNECT: Read DTMCS get 0x40b1.
CONNECT: DM is implemented depends on spec 0.13 as DTMCS.version is 1.
CONNECT: Get abits 11.
CONNECT: Get idle delay 4.
CONNECT: +--Attempt to connect Debug Module Spec 0.13.--+
CONNECT: Try to connect the 1st debug module with base 0x0.
CONNECT: Set DM Base to 0x0
CONNECT: Reset DM first:
CONNECT: Write DMCONTROL with 0 to make DM into a known state.
CONNECT: Write hasel, hartselhi, hartsello, dmactive all fileds in DMCONTROL with 1.
CONNECT: Read DMCONTROL get 0x4000001.
CONNECT: Check bit domain in DMCONTROL.
CONNECT: DMCONTROL.dmactive is 1, normal.
CONNECT: DMCONTROL.hasel is supported.
CONNECT: Get HARTSELLEN is 0.
CONNECT: Check DMSTATUS.
CONNECT: Read DMSTATUS get 0x4c0ca2, dm version is 2.
CONNECT: Get NextDM.
CONNECT: Read NEXTDM get 0x400.
CONNECT: Set dm_base to 0x0 for the 1st dm.
CONNECT: DM has been authenticated.
CONNECT: Hasresethaltreq is supported.
CONNECT: Confstrptrvalid is not valid.
CONNECT: Impebreak is supported.
CONNECT: Check SBCS.
CONNECT: Read SBCS get 0x0.
CONNECT: System bus access is not supported.
CONNECT: Check ABSTRACTCS.
CONNECT: Read ABSTRACTCS get 0x2000002.
CONNECT: Get progbufsize 2, datacount 2.
CONNECT: Check ABSTRACTAUTO.
CONNECT: Read ABSTRACTAUTO get 0x0.
CONNECT: Write ABSTRACTAUTO with 0xffffffff.
CONNECT: Read ABSTRACTAUTO get 0xffff0fff.
CONNECT: Autoexecprogbuf is supported.
CONNECT: Autoexecdata is supported.
CONNECT: Write ABSTRACTAUTO with 0x0.
CONNECT: Check CPU count.
CONNECT: Select to CPU 0 in 1st dm.
CONNECT: Write DM CONTROL with 0x1.
CONNECT: Read DM STATUS get 0x4c0ca2, CONNECT: CPU 0 in 1st dm exists.
CONNECT: Read DM HARTINFO get 0x200000.
CONNECT: Get nscrash 2, dataaccess 0, datasize 0, dataaddr 0x0.
CONNECT: Select to CPU 1 in 1st dm.
CONNECT: Write DM CONTROL with 0x10001.
CONNECT: Select to CPU 1 in 1st dm failed as not hartsel can't write with 1.
CONNECT: Try to connect the 2nd debug module with base 0x400.
CONNECT: Set DM Base to 0x400
CONNECT: Reset DM first:
CONNECT: Write DMCONTROL with 0 to make DM into a known state.
CONNECT: Write hasel, hartselhi, hartsello, dmactive all fileds in DMCONTROL with 1.
CONNECT: Read DMCONTROL get 0x4000001.
CONNECT: Check bit domain in DMCONTROL.
CONNECT: DMCONTROL.dmactive is 1, normal.
CONNECT: DMCONTROL.hasel is supported.
CONNECT: Get HARTSELLEN is 0.
CONNECT: Check DMSTATUS.
CONNECT: Read DMSTATUS get 0x4030a2, dm version is 2.
CONNECT: Get NextDM.
CONNECT: Read NEXTDM get 0x0.
CONNECT: Set dm_base to 0x400 for the 2nd dm.
CONNECT: DM has been authenticated.
CONNECT: Hasresethaltreq is supported.
CONNECT: Confstrptrvalid is not valid.
CONNECT: Impebreak is supported.
CONNECT: Check SBCS.
CONNECT: Read SBCS get 0x0.
CONNECT: System bus access is not supported.
CONNECT: Check ABSTRACTCS.
CONNECT: Read ABSTRACTCS get 0x2000002.
CONNECT: Get progbufsize 2, datacount 2.
CONNECT: Check ABSTRACTAUTO.
CONNECT: Read ABSTRACTAUTO get 0x0.
CONNECT: Write ABSTRACTAUTO with 0xffffffff.
CONNECT: Read ABSTRACTAUTO get 0xffff0fff.
CONNECT: Autoexecprogbuf is supported.
CONNECT: Autoexecdata is supported.
CONNECT: Write ABSTRACTAUTO with 0x0.
CONNECT: Check CPU count.
CONNECT: Select to CPU 0 in 2nd dm.
CONNECT: Write DM CONTROL with 0x1.
CONNECT: Read DM STATUS get 0x4030a2, CONNECT: CPU 0 in 2nd dm exists.
CONNECT: Read DM HARTINFO get 0x200000.
CONNECT: Get nscrash 2, dataaccess 0, datasize 0, dataaddr 0x0.
CONNECT: Select to CPU 1 in 2nd dm.
CONNECT: Write DM CONTROL with 0x10001.
CONNECT: Select to CPU 1 in 2nd dm failed as not hartsel can't write with 1.
CONNECT: +--Check cores.--+
CONNECT: Get low target with spec 0.13.
CONNECT: Check infomations of every RISCV core.
CONNECT: Select to CPU 0.
CONNECT: As multi-cores, set debug module base to 0x0.
CONNECT: Make CPU 0 into debug-mode.
CONNECT: As multi-cores, set debug module base to 0x0.
CONNECT: Check xlen for CPU 0.
CONNECT: Get xlen 64.
CONNECT: Read misa get: 0xb4112d.
CONNECT: Enumerate triggers.
CONNECT: Get hwbkpt 4, wp 4.
CONNECT: Set endian little(Always).
CONNECT: Read CPUID.
CONNECT: Read Marchid get:0x910090d.
CONNECT: Try to get vlen and elen: CONNECT: vlen=128, elen=3().
CONNECT: Analyzing CPUID gets info:
RISCV CPU Info:
WORD[0]: 0x0910090d
WORD[1]: 0x12046000
WORD[2]: 0x260c0001
WORD[3]: 0x30030076
WORD[4]: 0x42180000
WORD[5]: 0x50000000
WORD[6]: 0x60000853
MISA : 0x8000000000b4112d
Target Chip Info:
CPU Type is C906FDV, Endian=Little, Vlen=128, Version is R2S1P6.
DCache size is 64K, 4-Way Set Associative, Line Size is 64Bytes, with no ECC.
ICache size is 32K, 2-Way Set Associative, Line Size is 64Bytes, with no ECC.
Target is 1 core.
MMU has 256 JTLB items.
PMP zone num is 8.
HWBKPT number is 4, HWWP number is 4.
MISA: (RV64IMAFDCVX, Imp M-mode, S-mode, U-mode)
CONNECT: Get SATP.mode: CONNECT: 8
CONNECT: Get target-description info from xml file: /usr/bin/T-HEAD_DebugServer/tdescriptions/riscv/riscv-c906fdv-vlen128-tdesc.xml.
CONNECT: Select to CPU 1.
CONNECT: As multi-cores, set debug module base to 0x400.
CONNECT: Make CPU 1 into debug-mode.
CONNECT: As multi-cores, set debug module base to 0x400.
ERROR: CPU_1: Fail to enter debug mode.
WARNING: CPU_1: DMSTATUS is 0x4030a2, interpret as:
NdmResetPending: 0, StickyUnavail: 0, ImpEbreak: 1, AllHaveReset: 0
AnyHaveReset: 0 AllResumeAck: 0, AnyResumeAck: 0, AllNonexitent: 0
AnyNonexistent: 0, AllUnavail: 1, AnyUnavail: 1, AllRunning: 0
AnyRunning: 0, AllHalted: 0, AnyHalted: 0, Authenticated: 1
AuthBusy: 0, Hasresethaltreq: 1, Confstrptrvalid: 0, Version: 2.
CONNECT: Select to CPU to group cur.
CONNECT: As multi-cores, set debug module base to 0x0.
+-- Debug Arch is RVDM. --+
CONNECT: +--Get riscv_arch ops, executing arch_ops_init.--+
CONNECT: Executing riscv_ops_init.
CONNECT: Select to CPU 0.
CONNECT: As multi-cores, set debug module base to 0x0.
CONNECT: Invalid icache & dcache.
CONNECT: Escape CPU 1 as it is not normal.
CONNECT: Set current cpu to the first which is normal.
CONNECT: Set current cpu to 0.
CONNECT: As multi-cores, set debug module base to 0x0.
+-- CPU 0 --+
RISCV CPU Info:
WORD[0]: 0x0910090d
WORD[1]: 0x12046000
WORD[2]: 0x260c0001
WORD[3]: 0x30030076
WORD[4]: 0x42180000
WORD[5]: 0x50000000
WORD[6]: 0x60000853
MISA : 0x8000000000b4112d
Target Chip Info:
CPU Type is C906FDV, Endian=Little, Vlen=128, Version is R2S1P6.
DCache size is 64K, 4-Way Set Associative, Line Size is 64Bytes, with no ECC.
ICache size is 32K, 2-Way Set Associative, Line Size is 64Bytes, with no ECC.
Target is 1 core.
MMU has 256 JTLB items.
PMP zone num is 8.
HWBKPT number is 4, HWWP number is 4.
MISA: (RV64IMAFDCVX, Imp M-mode, S-mode, U-mode)
CONNECT: Connect target end(Leave target_open).
GDB connection command for CPUs(CPU0):
target remote 127.0.0.1:1025
target remote 192.168.2.18:1025
target remote 172.17.0.1:1025
**************** DebuggerServer Commands List **************
help/h
Show help informations.
*************************************************************
DebuggerServer$
```

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