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Added cl_khr_fp16 extension support for test_op_vector_extract from s…
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…pirv_new (issue KhronosGroup#142)
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@shajder
shajder committed Jun 16, 2023
1 parent 475a37a commit ccb864e
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Showing 4 changed files with 114 additions and 19 deletions.
42 changes: 42 additions & 0 deletions test_conformance/spirv_new/spirv_asm/vector_half8_extract.spvasm32
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; SPIR-V
; Version: 1.0
; Generator: Khronos SPIR-V Tools Assembler; 0
; Bound: 22
; Schema: 0
OpCapability Addresses
OpCapability Linkage
OpCapability Kernel
OpCapability Vector16
OpCapability Float16
OpMemoryModel Physical32 OpenCL
OpEntryPoint Kernel %1 "vector_half8_extract" %gl_GlobalInvocationID
OpName %in "in"
OpDecorate %gl_GlobalInvocationID BuiltIn GlobalInvocationId
OpDecorate %gl_GlobalInvocationID Constant
OpDecorate %in FuncParamAttr NoCapture
OpDecorate %4 FuncParamAttr NoCapture
OpDecorate %gl_GlobalInvocationID LinkageAttributes "__spirv_GlobalInvocationId" Import
%uint = OpTypeInt 32 0
%v3uint = OpTypeVector %uint 3
%_ptr_Input_v3uint = OpTypePointer Input %v3uint
%void = OpTypeVoid
%half = OpTypeFloat 16
%v8half = OpTypeVector %half 4
%_ptr_CrossWorkgroup_half = OpTypePointer CrossWorkgroup %half
%_ptr_CrossWorkgroup_v8half = OpTypePointer CrossWorkgroup %v8half
%13 = OpTypeFunction %void %_ptr_CrossWorkgroup_v8half %_ptr_CrossWorkgroup_half %uint
%gl_GlobalInvocationID = OpVariable %_ptr_Input_v3uint Input
%1 = OpFunction %void None %13
%in = OpFunctionParameter %_ptr_CrossWorkgroup_v8half
%4 = OpFunctionParameter %_ptr_CrossWorkgroup_half
%14 = OpFunctionParameter %uint
%15 = OpLabel
%16 = OpLoad %v3uint %gl_GlobalInvocationID Aligned 0
%17 = OpCompositeExtract %uint %16 0
%18 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_v8half %in %17
%19 = OpLoad %v8half %18
%20 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_half %4 %17
%21 = OpVectorExtractDynamic %half %19 %14
OpStore %20 %21
OpReturn
OpFunctionEnd
47 changes: 47 additions & 0 deletions test_conformance/spirv_new/spirv_asm/vector_half8_extract.spvasm64
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; SPIR-V
; Version: 1.0
; Generator: Khronos SPIR-V Tools Assembler; 0
; Bound: 26
; Schema: 0
OpCapability Addresses
OpCapability Linkage
OpCapability Kernel
OpCapability Int64
OpCapability Vector16
OpCapability Float16
OpMemoryModel Physical64 OpenCL
OpEntryPoint Kernel %1 "vector_half8_extract" %gl_GlobalInvocationID
OpName %in "in"
OpDecorate %gl_GlobalInvocationID BuiltIn GlobalInvocationId
OpDecorate %gl_GlobalInvocationID Constant
OpDecorate %in FuncParamAttr NoCapture
OpDecorate %4 FuncParamAttr NoCapture
OpDecorate %gl_GlobalInvocationID LinkageAttributes "__spirv_GlobalInvocationId" Import
%ulong = OpTypeInt 64 0
%v3ulong = OpTypeVector %ulong 3
%_ptr_Input_v3ulong = OpTypePointer Input %v3ulong
%ulong_32 = OpConstant %ulong 32
%uint = OpTypeInt 32 0
%void = OpTypeVoid
%half = OpTypeFloat 16
%v8half = OpTypeVector %half 8
%_ptr_CrossWorkgroup_half = OpTypePointer CrossWorkgroup %half
%_ptr_CrossWorkgroup_v8half = OpTypePointer CrossWorkgroup %v8half
%15 = OpTypeFunction %void %_ptr_CrossWorkgroup_v8half %_ptr_CrossWorkgroup_half %uint
%gl_GlobalInvocationID = OpVariable %_ptr_Input_v3ulong Input
%1 = OpFunction %void None %15
%in = OpFunctionParameter %_ptr_CrossWorkgroup_v8half
%4 = OpFunctionParameter %_ptr_CrossWorkgroup_half
%16 = OpFunctionParameter %uint
%17 = OpLabel
%18 = OpLoad %v3ulong %gl_GlobalInvocationID Aligned 0
%19 = OpCompositeExtract %ulong %18 0
%20 = OpShiftLeftLogical %ulong %19 %ulong_32
%21 = OpShiftRightArithmetic %ulong %20 %ulong_32
%22 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_v8half %in %21
%23 = OpLoad %v8half %22
%24 = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_half %4 %21
%25 = OpVectorExtractDynamic %half %23 %16
OpStore %24 %25
OpReturn
OpFunctionEnd
41 changes: 22 additions & 19 deletions test_conformance/spirv_new/test_op_vector_extract.cpp
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Expand Up @@ -76,27 +76,30 @@ int test_extract(cl_device_id deviceID, cl_context context,
return 0;
}

#define TEST_VECTOR_EXTRACT(TYPE, N) \
TEST_SPIRV_FUNC(op_vector_##TYPE##N##_extract) \
{ \
typedef cl_##TYPE##N Tv; \
typedef cl_##TYPE Ts; \
const int num = 1 << 20; \
std::vector<Tv> in(num); \
const char *name = "vector_" #TYPE #N "_extract"; \
\
RandomSeed seed(gRandomSeed); \
\
for (int i = 0; i < num; i++) { \
in[i] = genrand<Tv>(seed); \
} \
\
return test_extract<Tv, Ts>(deviceID, \
context, queue, \
name, \
in, N); \
#define TEST_VECTOR_EXTRACT(TYPE, N) \
TEST_SPIRV_FUNC(op_vector_##TYPE##N##_extract) \
{ \
if (sizeof(cl_##TYPE) == 2) \
{ \
PASSIVE_REQUIRE_FP16_SUPPORT(deviceID); \
} \
typedef cl_##TYPE##N Tv; \
typedef cl_##TYPE Ts; \
const int num = 1 << 20; \
std::vector<Tv> in(num); \
const char *name = "vector_" #TYPE #N "_extract"; \
\
RandomSeed seed(gRandomSeed); \
\
for (int i = 0; i < num; i++) \
{ \
in[i] = genrand<Tv>(seed); \
} \
\
return test_extract<Tv, Ts>(deviceID, context, queue, name, in, N); \
}

TEST_VECTOR_EXTRACT(half, 8)
TEST_VECTOR_EXTRACT(int, 4)
TEST_VECTOR_EXTRACT(float, 4)
TEST_VECTOR_EXTRACT(long, 2)
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3 changes: 3 additions & 0 deletions test_conformance/spirv_new/types.hpp
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Expand Up @@ -109,6 +109,9 @@ GENRAND_REAL_FUNC(cl_float, 2)
GENRAND_REAL_FUNC(cl_float, 4)
GENRAND_REAL_FUNC(cl_double, 2)
GENRAND_REAL_FUNC(cl_double, 4)
GENRAND_REAL_FUNC(cl_half, 2)
GENRAND_REAL_FUNC(cl_half, 4)
GENRAND_REAL_FUNC(cl_half, 8)

template<> inline cl_half genrandReal<cl_half>(RandomSeed &seed)
{
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