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Add support for using SymbiFlow open source tooling instead of Vivado
#54
opened Aug 4, 2021 by
mithro
Provide method to add user-defined synthesis/implementation constraints
#49
opened Jul 13, 2021 by
sgherbst
Provide method to get UART port / PySerial object without programming FPGA
#48
opened Jun 5, 2021 by
sgherbst
Provide method to treat *.v files as SystemVerilog files in Vivado
#43
opened Jan 28, 2021 by
sgherbst
Duplicated time points in waveforms from simulation and emulation
#11
opened Apr 25, 2020 by
sgherbst
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