Skip to content

sempfi/MIPS

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

6 Commits
iseconfig
iseconfig
 
 
EX_MEM_reg.bmm
EX_MEM_reg.bmm
 
 
EX_MEM_reg.cmd_log
EX_MEM_reg.cmd_log
 
 
EX_MEM_reg.v
EX_MEM_reg.v
 
 
EX_MEM_reg_test.v
EX_MEM_reg_test.v
 
 
ID_EX_reg.cmd_log
ID_EX_reg.cmd_log
 
 
ID_EX_reg.v
ID_EX_reg.v
 
 
ID_EX_reg_test.v
ID_EX_reg_test.v
 
 
ID_EX_reg_test_beh.prj
ID_EX_reg_test_beh.prj
 
 
IF_ID_reg.cmd_log
IF_ID_reg.cmd_log
 
 
IF_ID_reg.v
IF_ID_reg.v
 
 
IF_ID_reg_test.v
IF_ID_reg_test.v
 
 
IF_ID_reg_test_isim_beh1.wdb
IF_ID_reg_test_isim_beh1.wdb
 
 
MEM_WB_reg.cmd_log
MEM_WB_reg.cmd_log
 
 
MEM_WB_reg.v
MEM_WB_reg.v
 
 
MEM_WB_reg_test.v
MEM_WB_reg_test.v
 
 
MIPS.gise
MIPS.gise
 
 
MIPS.sym
MIPS.sym
 
 
MIPS.v
MIPS.v
 
 
MIPS.xise
MIPS.xise
 
 
MIPS_summary.html
MIPS_summary.html
 
 
MIPS_test.v
MIPS_test.v
 
 
MUX_32bits.cmd_log
MUX_32bits.cmd_log
 
 
MUX_32bits.v
MUX_32bits.v
 
 
MUX_32bits_summary.html
MUX_32bits_summary.html
 
 
MUX_32bits_test.v
MUX_32bits_test.v
 
 
MUX_3_8.cmd_log
MUX_3_8.cmd_log
 
 
MUX_3_8.v
MUX_3_8.v
 
 
README.md
README.md
 
 
alu.cmd_log
alu.cmd_log
 
 
alu.v
alu.v
 
 
alu_control.cmd_log
alu_control.cmd_log
 
 
alu_control.v
alu_control.v
 
 
alu_control_test.v
alu_control_test.v
 
 
alu_coontrol_test.v
alu_coontrol_test.v
 
 
alu_test.v
alu_test.v
 
 
cache.cmd_log
cache.cmd_log
 
 
cache.lso
cache.lso
 
 
cache.v
cache.v
 
 
cache_test.v
cache_test.v
 
 
control_unit.cmd_log
control_unit.cmd_log
 
 
control_unit.lso
control_unit.lso
 
 
control_unit.v
control_unit.v
 
 
control_unit_test.v
control_unit_test.v
 
 
data_memory.cmd_log
data_memory.cmd_log
 
 
data_memory.v
data_memory.v
 
 
data_memory_test.v
data_memory_test.v
 
 
decode_module.cmd_log
decode_module.cmd_log
 
 
decode_module.v
decode_module.v
 
 
decode_module_guide.ncd
decode_module_guide.ncd
 
 
decode_module_test.v
decode_module_test.v
 
 
execute_module.cmd_log
execute_module.cmd_log
 
 
execute_module.v
execute_module.v
 
 
execute_module_test.v
execute_module_test.v
 
 
execute_module_test_isim_beh1.wdb
execute_module_test_isim_beh1.wdb
 
 
fetch_module.cmd_log
fetch_module.cmd_log
 
 
fetch_module.sym
fetch_module.sym
 
 
fetch_module.v
fetch_module.v
 
 
fetch_module_summary.html
fetch_module_summary.html
 
 
fetch_module_test.v
fetch_module_test.v
 
 
fuse.xmsgs
fuse.xmsgs
 
 
fuseRelaunch.cmd
fuseRelaunch.cmd
 
 
inst_mem.cmd_log
inst_mem.cmd_log
 
 
inst_mem.v
inst_mem.v
 
 
inst_mem_test.v
inst_mem_test.v
 
 
inst_mem_test_isim_beh1.wdb
inst_mem_test_isim_beh1.wdb
 
 
instruction_memory.txt
instruction_memory.txt
 
 
instructions_opcode
instructions_opcode
 
 
par_usage_statistics.html
par_usage_statistics.html
 
 
pc_reg.cmd_log
pc_reg.cmd_log
 
 
pc_reg.v
pc_reg.v
 
 
pc_reg_test.v
pc_reg_test.v
 
 
reg_file.cmd_log
reg_file.cmd_log
 
 
reg_file.v
reg_file.v
 
 
reg_file_test.v
reg_file_test.v
 
 
registers.txt
registers.txt
 
 
sign_extend.cmd_log
sign_extend.cmd_log
 
 
sign_extend.v
sign_extend.v
 
 
sign_extend_test.v
sign_extend_test.v
 
 
wite_back.cmd_log
wite_back.cmd_log
 
 
write_back.v
write_back.v
 
 
write_back_test.v
write_back_test.v
 
 
write_back_test_isim_beh1.wdb
write_back_test_isim_beh1.wdb
 
 
write_back_test_isim_beh2.wdb
write_back_test_isim_beh2.wdb
 
 

Repository files navigation

MIPS

This is the MIPS architecture implemented in Verilog. This was the project for the course "Computer Architecture Lab" at Shiraz University, Fall 2021.

The supported instructions are listed (along with their opcodes) in the "instructions_opcode" file.

About

MIPS architecture implemented in Verilog.

Resources

Readme
Activity

Stars

2 stars

Watchers

1 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages