riscy

A RISC-V processor.

Originally part of my project weekcore, now a more in depth computer architecture exercise.

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
TODO		TODO
cpu.v		cpu.v
notes		notes
test.sh		test.sh
test_ctrl.v		test_ctrl.v
test_pc.v		test_pc.v
test_ram.v		test_ram.v
test_regfile.v		test_regfile.v

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