Get Icarus Verilog, then:
$ python3 asm/asm.py
$ ./rtl/test.sh
add
sub
and
or
slt
lw
sw
beq
- D. Harris & S. Harris, Digital Design and Computer Architecture, 2nd Ed., Waltham, MA: Morgan Kaufmann, 2013
- MIPS32® Architecture For Programmers Volume II: The MIPS32® Instruction Set