Address https://github.com/riscv/riscv-debug-spec/issues/985

Sdtrig.adoc

@@ -118,7 +118,7 @@ Instruction address misaligned +
 Environment call +
 Environment break +
 Load/Store/AMO address breakpoint
-.>| mcontrol/mcontrol6 load/store address/data before
+.>| mcontrol/mcontrol6 load/store address before, store data before
 || 4, 6 | Optionally: Load/Store/AMO address misaligned |
 || 13, 15, 21, 23, 5, 7 | During address translation for an explicit
 memory access: First encountered page fault, guest-page fault, or access
@@ -370,4 +370,4 @@ trigger firing at a different time than is expected.
 Attempts to access an unimplemented Trigger Module Register raise an illegal
 instruction exception.
 
-include::build/hwbp_registers.adoc[]
+include::build/hwbp_registers.adoc[]

debug_module.adoc

@@ -149,7 +149,7 @@ simultaneously. The state of the hart array mask register is not
 affected by setting or clearing {dmcontrol-hasel}.
 
 Execution of Abstract Commands ignores this mechanism and only applies
-to the hart selected by {dmstatus-hartsello}.
+to the hart selected by {hartsel}.
 
 === Hart DM States
 

introduction.adoc

@@ -40,7 +40,8 @@ functionality.
 
 *DTM*:: Debug Transport Module (see <<dtm>>).
 
-*DXLEN*:: Debug XLEN, which is the widest XLEN a hart supports, ignoring the current value of in .
+*DXLEN*:: Debug XLEN, which is the widest XLEN a hart supports, ignoring the
+current value of `mxl` in `misa`.
 
 *essential feature*:: An essential feature must be present in order for debug to work correctly.
 

xml/hwbp_registers.xml

@@ -731,7 +731,7 @@ same project unless stated otherwise.
 
         [NOTE]
         ====
-        {mcontrol6-uncertain} and {mcontrol6-uncertain}en exist to
+        {mcontrol6-uncertain} and {mcontrol6-uncertainen} exist to
         accommodate systems where not every memory access is fully observed by
         the Trigger Module. Possible examples include data values in far AMOs,
         and the address/data/size of accesses by instructions that perform