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riscv / riscv-debug-spec Public

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Make the data of the *context registers 32 bits wide.#981

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rtwfroody merged 2 commits intorc2riscv/riscv-debug-spec:rc2from contextriscv/riscv-debug-spec:contextCopy head branch name to clipboard

Mar 19, 2024

+26-14

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Commits on Mar 18, 2024

Make the data of the *context registers 32 bits wide.
rtwfroody
committed
In Sdtrig, XLEN refers to the current mode.
rtwfroody
committed

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