Integrated ratified Zicfilp extension

Sdext.adoc

@@ -62,6 +62,9 @@ acts as an illegal instruction, all such instructions must act as
 illegal instructions.
 . Instructions that depend on the value of the PC (e.g. `auipc`) may act
 as illegal instructions.
+. When the Zicfilp extension is implemented, the `ELP` state is
+  `NO_LP_EXPECTED` and is not updated by any instructions. LPAD instruction
+  executes as a no-op.
 . Effective XLEN is DXLEN.
 . Forward progress is guaranteed.
 
@@ -176,6 +179,8 @@ When a hart halts:
 
 . {dcsr-cause} is updated.
 . {dcsr-prv} and {dcsr-v} are set to reflect current privilege mode and virtualization mode.
+. If the Zicfilp extension is implemented, {dcsr-pelp} is set to the current
+  `ELP` state and `ELP` is set to `NO_LP_EXPECTED`
 . {csr-dpc} is set to the next instruction that should be executed.
 . If the current instruction can be partially executed and should be
 restarted to complete, then the relevant state for that is updated. E.g.
@@ -191,6 +196,9 @@ When a hart resumes:
 . `pc` changes to the value stored in {csr-dpc}.
 . The current privilege mode and virtualization mode are changed to that
 specified by {dcsr-prv} and {dcsr-v}.
+. If the Zicfilp extension is enabled at the new privilege mode, the current
+  `ELP` state is changed to that specified by {dcsr-pelp} else it is set to
+  `NO_LP_EXPECTED`. {dcsr-pelp} is set to `NO_LP_EXPECTED`.
 . If the new privilege mode is less privileged than M-mode, `MPRV` in `mstatus` is cleared.
 . If the Smdbltrp extension is implemented and the new privilege mode is not M,
   then the `MDT` bit is set to 0.

implementations.adoc

@@ -65,7 +65,8 @@ To resume execution, the debug module sets a flag which causes the hart
 to execute a `dret`. `dret` is an instruction that only has meaning
 while in Debug Mode and not executing from the Program Buffer. Its
 recommended encoding is 0x7b200073. When `dret` is executed, is restored
-from {csr-dpc} and normal execution resumes at the privilege set by {dcsr-prv} and {dcsr-v}.
+from {csr-dpc} and normal execution resumes at the privilege set by {dcsr-prv} and {dcsr-v},
+and the ELP state set by {dcsr-pelp}.
 
 {dm-data0} etc. are mapped into regular memory at an address relative to with only
 a 12-bit `imm`. The exact address is an implementation detail that a

introduction.adoc

@@ -43,6 +43,8 @@ functionality.
 *DXLEN*:: Debug XLEN, which is the widest XLEN a hart supports, ignoring the
 current value of `mxl` in `misa`.
 
+*ELP*:: Expected landing pad state, define by the Zicfilp extension.
+
 *essential feature*:: An essential feature must be present in order for debug to work correctly.
 
 *GPR*:: General Purpose Register.

xml/core_registers.xml

@@ -115,7 +115,16 @@ same project unless stated otherwise.
                 reset using the Debug Module reset control.
             ====
         </field>
-        <field name="0" bits="18" access="R" reset="0" />
+        <field name="pelp" bits="18" access="WARL" reset="0">
+            This bit is part of ((Zicfilp)) and only exists when that extension
+            is implemented.
+            <value v="0" name="NO_LP_EXPECTED">
+                No landing pad instruction expected.
+            </value>
+            <value v="1" name="LP_EXPECTED">
+                A landing pad instruction is expected.
+            </value>
+        </field>
         <field name="ebreakvs" bits="17" access="WARL" reset="0">
             <value v="0" name="exception">
             `ebreak` instructions in VS-mode behave as described in the