AR: Define mcontrol* triggers and multiple accesses

mcontrol: Behavior is undefined because it's deprecated.

mcontrol6: If a trigger reports hit=before then some memory accesses may
have been performed. If it reports immediately after, then all accesses
have already been performed.

xml/hwbp_registers.xml

@@ -378,6 +378,9 @@
             though the load will not update its destination register. Debuggers
             should consider this when setting such breakpoints on, for example,
             memory-mapped I/O addresses.
+
+            It is \unspecified what should happen when the instruction in question
+            performs multiple memory accesses.
             </value>
 
             <value v="1" name="after">
@@ -746,6 +749,12 @@
             \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set
             to the virtual address of the instruction that matched.
 
+            If an instruction partially executed, the reported timing is still
+            before. This might mean that when the instruction is executed again
+            it will perform some of the same stores again (e.g. \tt{cbo.zero}),
+            or the instruction might have a mechanism that avoids duplicating the
+            stores (e.g. vector stores and the vstart mechanism).
+
             If a load operation matched and \FcsrMcontrolSixSelect=1 then a
             memory access has been performed (including any side effects of
             performing such an access) even though the load has not updated its
@@ -766,6 +775,9 @@
             \Rxepc or \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set
             to the virtual address of the next instruction that must be executed
             to preserve the program flow.
+
+            If the instruction performed multiple memory accesses, all of them
+            have been completed.
             </value>
         </field>
         <field name="select" bits="21" access="WARL" reset="0">