AR: Clarify why icount matches on every trap.

Sdext.tex

@@ -141,7 +141,7 @@ \subsection{Step Bit In Dcsr} \label{stepBit}
 instead the instruction is treated as a {\tt nop}. This includes {\tt wfi},
 {\tt wrs.sto}, and {\tt wrs.nto}.
 
-\subsection{Icount Trigger}
+\subsection{Icount Trigger} \label{stepIcount}
 
 Native debuggers won't have access to \RcsrDcsr, but can use the \RcsrIcount
 trigger by setting \FcsrIcountCount to 1.

xml/hwbp_registers.xml

@@ -1009,6 +1009,14 @@
         If more than one of the above events occur during a single instruction
         execution, the trigger still only matches once for that instruction.
 
+        \begin{commentary}
+            For use in single step, ideally you want icount to match for e.g.
+            and illegal instruction trap, but not for a page fault (assuming
+            that the handler will add a PTE). That leads to complex rules, so
+            instead the rule is simply that all traps match. See also
+            Section~\ref{stepIcount}.
+        \end{commentary}
+
         When \FcsrIcountCount is greater than 1 and the trigger matches, then
         \FcsrIcountCount is decremented by 1.