Merge branch 'issue985' of github.com:pdonahue-ventana/riscv-debug-sp…

…ec into issue985
riscv · Mar 21, 2024 · b60b1b8 · b60b1b8
2 parents 82e0b9a + 501da2c
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diff --git a/debug_module.adoc b/debug_module.adoc
@@ -149,7 +149,7 @@ simultaneously. The state of the hart array mask register is not
 affected by setting or clearing {dmcontrol-hasel}.
 
 Execution of Abstract Commands ignores this mechanism and only applies
-to the hart selected by {dmstatus-hartsello}.
+to the hart selected by {hartsel}.
 
 === Hart DM States
 

diff --git a/introduction.adoc b/introduction.adoc
@@ -40,7 +40,8 @@ functionality.
 
 *DTM*:: Debug Transport Module (see <<dtm>>).
 
-*DXLEN*:: Debug XLEN, which is the widest XLEN a hart supports, ignoring the current value of in .
+*DXLEN*:: Debug XLEN, which is the widest XLEN a hart supports, ignoring the
+current value of `mxl` in `misa`.
 
 *essential feature*:: An essential feature must be present in order for debug to work correctly.
 

diff --git a/xml/hwbp_registers.xml b/xml/hwbp_registers.xml
@@ -731,7 +731,7 @@ same project unless stated otherwise.
 
         [NOTE]
         ====
-        {mcontrol6-uncertain} and {mcontrol6-uncertain}en exist to
+        {mcontrol6-uncertain} and {mcontrol6-uncertainen} exist to
         accommodate systems where not every memory access is fully observed by
         the Trigger Module. Possible examples include data values in far AMOs,
         and the address/data/size of accesses by instructions that perform