Clarify Memory Access acts like data access.

I'm not sure if this is necessary. Does RISC-V allow data loads to
differ from instruction fetches? For a long time any mention of caches
was avoided in all specs.

Inspired by #1062.

xml/abstract_commands.xml

@@ -181,7 +181,10 @@ same project unless stated otherwise.
         This command lets the debugger perform memory accesses,
             with the exact same memory view and permissions as the selected
             hart has. This includes access to hart-local memory-mapped
-            registers, etc. The command performs the following sequence of
+            registers, etc.
+            If the hart treats instruction fetches different from data loads,
+            then Access Memory gets the data load behavior.
+            The command performs the following sequence of
             operations:
 
         . Copy data from the memory location specified in `arg1` into the