Merge pull request #936 from riscv/references

Clean up remaining LaTeX register/field macros.
riscv · Dec 22, 2023 · 49d1c04 · 49d1c04
2 parents 65623a7 + acadd27
commit 49d1c04
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/debugger_implementation.adoc b/debugger_implementation.adoc
@@ -472,7 +472,7 @@ tricky to get right. To single step, the debug stub would execute
 something like:
 
 ....
-    li    t0, \FcsrIcountCount=4, \FcsrIcountAction=0, \FcsrIcountM=1
+    li    t0, {icount-count}=4, {icount-action}=0, {icount-m}=1
     csrw  tdata1, t0    /* Write the trigger. */
     lw    t0, 8(sp)     /* Restore t0, count decrements to 3 */
     lw    sp, 0(sp)     /* Restore sp, count decrements to 2 */

diff --git a/dm_registers.adoc b/dm_registers.adoc
@@ -571,8 +571,8 @@ with 48 harts only bit 0 of this field may actually be writable. |WARL
 the hart array mask register (see
 Section link:#hartarraymask[[hartarraymask]]). The position of the
 window is determined by . I.e. bit 0 refers to hart
-latexmath:[$\RdmHawindowsel * 32$], while bit 31 refers to hart
-latexmath:[$\RdmHawindowsel * 32 + 31$].
+latexmath:[${dm-hawindowsel} * 32$], while bit 31 refers to hart
+latexmath:[${dm-hawindowsel} * 32 + 31$].
 
 Since some bits in the hart array mask register may be constant 0, some
 bits in this register may be constant 0, depending on the current value

diff --git a/riscv-debug-spec.adoc b/riscv-debug-spec.adoc
@@ -1550,8 +1550,8 @@ may actually be writable. & WARL & 0 +
 [#dmHawindow]## This register provides R/W access to a 32-bit portion of
 the hart array mask register (see Section link:#hartarraymask[4.3.2]).
 The position of the window is determined by . I.e. bit 0 refers to hart
-latexmath:[$\RdmHawindowsel * 32$], while bit 31 refers to hart
-latexmath:[$\RdmHawindowsel * 32 + 31$].
+latexmath:[${dm-hawindowsel} * 32$], while bit 31 refers to hart
+latexmath:[${dm-hawindowsel} * 32 + 31$].
 
 Since some bits in the hart array mask register may be constant 0, some
 bits in this register may be constant 0, depending on the current value
@@ -3765,7 +3765,7 @@ tricky to get right. To single step, the debug stub would execute
 something like:
 
 ....
-    li    t0, \FcsrIcountCount=4, \FcsrIcountAction=0, \FcsrIcountM=1
+    li    t0, {icount-count}=4, {icount-action}=0, {icount-m}=1
     csrw  tdata1, t0    /* Write the trigger. */
     lw    t0, 8(sp)     /* Restore t0, count decrements to 3 */
     lw    sp, 0(sp)     /* Restore sp, count decrements to 2 */