ECE 111 Spring 2014 Winning RLE Compression in Verilog

Winning RLE Compression Design in Verilog UCSD ECE 111 Spring 2014

05-12: For the RLE project, the top designs for Best Delay are:

1. Richard Bull & Michael Hughes:

ALUTs = 1019, #Registers = 165, Area = 1184
Clock period = 4.19 ns, Clock cycles = 55
Delay = 230 ns, Area*Delay = 2.72 x 10-4

http://cwc.ucsd.edu/~billlin/classes/ECE111/index.php

Part A & Part B are both the same design.