Update i915 PXP and MEI Driver to DII client.

drivers/gpu/drm/i915/gt/intel_gt.h

@@ -115,5 +115,4 @@ void intel_gt_info_print(const struct intel_gt_info *info,
 			 struct drm_printer *p);
 
 void intel_gt_watchdog_work(struct work_struct *work);
-
 #endif /* __INTEL_GT_H__ */

drivers/gpu/drm/i915/gt/iov/intel_iov_ggtt.c

@@ -52,7 +52,7 @@ static bool is_pte_replicable(struct intel_iov *iov, gen8_pte_t pte)
 int intel_iov_ggtt_vf_update_pte(struct intel_iov *iov, u32 offset, gen8_pte_t pte)
 {
 	struct intel_iov_vf_ggtt_ptes *buffer = &iov->vf.ptes_buffer;
-	u8 max_copies = FIELD_MAX(VF2PF_MMIO_UPDATE_GGTT_REQUEST_MSG_1_NUM_COPIES);
+	u8 max_copies = (u8)FIELD_MAX(VF2PF_MMIO_UPDATE_GGTT_REQUEST_MSG_1_NUM_COPIES);
 	u8 max_ptes = MMIO_UPDATE_GGTT_MAX_PTES;
 	u32 pte_offset = (offset >> PAGE_SHIFT) - (iov->vf.config.ggtt_base >> PAGE_SHIFT);
 
@@ -133,7 +133,7 @@ int intel_iov_ggtt_vf_update_pte(struct intel_iov *iov, u32 offset, gen8_pte_t p
 int intel_iov_ggtt_vf_flush_ptes(struct intel_iov *iov)
 {
 	struct intel_iov_vf_ggtt_ptes *buffer = &iov->vf.ptes_buffer;
-	int err;
+	int err = 0;
 
 	GEM_BUG_ON(!intel_iov_is_vf(iov));
 

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

@@ -58,6 +58,97 @@
 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN
 #define HOST2GUC_SELF_CFG_RESPONSE_MSG_0_NUM		GUC_HXG_RESPONSE_MSG_0_DATA0
 
+/**
+ * DOC: HOST2GUC_SET_ENGINE_SCHED
+ *
+ * This H2G action allows to start/stop scheduling on a class engines.
+ *
+ * This G2H message must be sent as `CTB HXG Message`_.
+ *
+ *  +---+-------+--------------------------------------------------------------+
+ *  |   | Bits  | Description                                                  |
+ *  +===+=======+==============================================================+
+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   | 27:16 | DATA0 = MBZ                                                  |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SET_ENGINE_SCHED` = 0x1003    |
+ *  +---+-------+--------------------------------------------------------------+
+ *  | 1 |  31:0 | **ENGINE_CLASS** - Engine Class for which the change in      |
+ *  |   |       |                    Scheduling State is requeste              |
+ *  +---+-------+--------------------------------------------------------------+
+ *  | 2 |  31:0 | **STATE** - new state value                                  |
+ *  |   |       |                                                              |
+ *  |   |       |   - _`GUC_SET_ENGINE_SCHED_STATE_DISABLE` = 0                |
+ *  |   |       |   - _`GUC_SET_ENGINE_SCHED_STATE_ENABLE` = 1                 |
+ *  +---+-------+--------------------------------------------------------------+
+ *  | 3 |  31:0 | **IMMEDIATE_MODE** - Immediate mode                          |
+ *  |   |       |                                                              |
+ *  |   |       |   - _`GUC_SET_ENGINE_SCHED_IMM_MODE_DISABLE` = 0             |
+ *  |   |       |   - _`GUC_SET_ENGINE_SCHED_IMM_MODE_ENABLE` = 1              |
+ *  +---+-------+--------------------------------------------------------------+
+ *
+ *  +---+-------+--------------------------------------------------------------+
+ *  |   | Bits  | Description                                                  |
+ *  +===+=======+==============================================================+
+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   |  27:0 | DATA0 = MBZ                                                  |
+ *  +---+-------+--------------------------------------------------------------+
+ */
+#define GUC_ACTION_HOST2GUC_SET_ENGINE_SCHED			0x1003
+
+#define HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
+#define HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0
+#define HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_1_ENGINE_CLASS	GUC_HXG_REQUEST_MSG_n_DATAn
+#define HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_2_STATE		GUC_HXG_REQUEST_MSG_n_DATAn
+#define   GUC_SET_ENGINE_SCHED_STATE_DISABLE				0u
+#define   GUC_SET_ENGINE_SCHED_STATE_ENABLE				1u
+#define HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_3_IMM_MODE	GUC_HXG_REQUEST_MSG_n_DATAn
+#define   GUC_SET_ENGINE_SCHED_IMM_MODE_DISABLE				0u
+#define   GUC_SET_ENGINE_SCHED_IMM_MODE_ENABLE				1u
+
+#define HOST2GUC_SET_ENGINE_SCHED_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN
+#define HOST2GUC_SET_ENGINE_SCHED_RESPONSE_MSG_0_MBZ		GUC_HXG_RESPONSE_MSG_0_DATA0
+
+/**
+ * DOC: GUC2HOST_SET_ENGINE_SCHED_DONE
+ *
+ * This message is used by the GuC to acknowledge enable/disable scheduling
+ * on particular Engine Class.
+ *
+ * This G2H message must be sent as `CTB HXG Message`_.
+ *
+ *  +---+-------+--------------------------------------------------------------+
+ *  |   | Bits  | Description                                                  |
+ *  +===+=======+==============================================================+
+ *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   | 30:28 | TYPE = GUC_HXG_TYPE_EVENT_                                   |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   | 27:16 | DATA0 = MBZ                                                  |
+ *  |   +-------+--------------------------------------------------------------+
+ *  |   |  15:0 | ACTION = _`GUC_ACTION_GUC2HOST_SET_ENGINE_SCHED_DONE` =      |
+ *  |   |       |          0x1004                                              |
+ *  +---+-------+--------------------------------------------------------------+
+ *  | 1 |  31:0 | **ENGINE_CLASS** - Engine Class for which the Scheduling was |
+ *  |   |       |                    enabled or disabled                       |
+ *  +---+-------+--------------------------------------------------------------+
+ *  | 2 |  31:0 | **IS_RUNNABLE** - Whether the Engines are made runnable or   |
+ *  |   |       |                   not                                        |
+ *  +---+-------+--------------------------------------------------------------+
+ */
+#define GUC_ACTION_GUC2HOST_SET_ENGINE_SCHED_DONE		0x1004
+
+#define GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_LEN			(GUC_HXG_EVENT_MSG_MIN_LEN + 2u)
+#define GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_0_MBZ		GUC_HXG_EVENT_MSG_0_DATA0
+#define GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_1_ENGINE_CLASS	GUC_HXG_EVENT_MSG_n_DATAn
+#define GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_2_IS_RUNNABLE	GUC_HXG_EVENT_MSG_n_DATAn
+
 /**
  * DOC: HOST2GUC_CONTROL_CTB
  *

drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h

@@ -12,6 +12,12 @@ struct i915_vma;
 struct intel_context;
 struct intel_gsc_uc;
 
+#define GSC_HECI_REPLY_LATENCY_MS 500
+/*
+ * Max FW response time is 500ms, but this should be counted from the time the
+ * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB.
+ */
+
 struct intel_gsc_mtl_header {
 	u32 validity_marker;
 #define GSC_HECI_VALIDITY_MARKER 0xA578875A

drivers/gpu/drm/i915/gt/uc/intel_guc.c

@@ -926,6 +926,34 @@ int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)
 	return __guc_self_cfg(guc, key, 2, value);
 }
 
+int intel_guc_enable_gsc_engine(struct intel_guc *guc)
+{
+	struct intel_gt *gt = guc_to_gt(guc);
+
+	if (!HAS_ENGINE(gt, GSC0))
+		return 0;
+
+	return intel_guc_set_engine_sched(guc, GUC_GSC_OTHER_CLASS, SET_ENGINE_SCHED_FLAGS_ENABLE);
+}
+
+int intel_guc_disable_gsc_engine(struct intel_guc *guc)
+{
+	struct intel_gt *gt = guc_to_gt(guc);
+	int err;
+
+	if (!HAS_ENGINE(gt, GSC0))
+		return 0;
+
+	if (wait_for(intel_engine_is_idle(gt->engine[GSC0]), I915_GEM_IDLE_TIMEOUT))
+		return -EBUSY;
+
+	err = intel_guc_set_engine_sched(guc, GUC_GSC_OTHER_CLASS, 0);
+	if (err < 0)
+		return err;
+
+	return __intel_gt_reset(gt, gt->engine[GSC0]->mask);
+}
+
 /**
  * intel_guc_load_status - dump information about GuC load status
  * @guc: the GuC

drivers/gpu/drm/i915/gt/uc/intel_guc.h

@@ -442,6 +442,8 @@ int intel_guc_invalidate_tlb_full(struct intel_guc *guc);
 int intel_guc_invalidate_tlb(struct intel_guc *guc);
 int intel_guc_tlb_invalidation_done(struct intel_guc *guc, const u32 *hxg,
 				    u32 size);
+int intel_guc_enable_gsc_engine(struct intel_guc *guc);
+int intel_guc_disable_gsc_engine(struct intel_guc *guc);
 
 static inline bool intel_guc_is_supported(const struct intel_guc *guc)
 {

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

@@ -1160,6 +1160,9 @@ static int ct_process_request(struct intel_guc_ct *ct, struct ct_incoming_msg *r
 	case INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:
 		ret = intel_guc_sched_done_process_msg(guc, payload, len);
 		break;
+	case GUC_ACTION_GUC2HOST_SET_ENGINE_SCHED_DONE:
+		ret = intel_guc_process_set_engine_sched_done(guc, hxg, hxg_len);
+		break;
 	case INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION:
 		ret = intel_guc_context_reset_process_msg(guc, payload, len);
 		break;
@@ -1268,6 +1271,7 @@ static int ct_handle_event(struct intel_guc_ct *ct, struct ct_incoming_msg *requ
 	 * circular dependency if the space was returned there.
 	 */
 	switch (action) {
+	case GUC_ACTION_GUC2HOST_SET_ENGINE_SCHED_DONE:
 	case INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE:
 	case INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE:
 	case INTEL_GUC_ACTION_TLB_INVALIDATION_DONE:

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

@@ -2939,6 +2939,40 @@ static void guc_context_post_unpin(struct intel_context *ce)
 	lrc_post_unpin(ce);
 }
 
+int intel_guc_set_engine_sched(struct intel_guc *guc, u32 class, u32 flags)
+{
+	u32 state = flags & SET_ENGINE_SCHED_FLAGS_ENABLE ?
+		    GUC_SET_ENGINE_SCHED_STATE_ENABLE : GUC_SET_ENGINE_SCHED_STATE_DISABLE;
+	u32 imm_mode = flags & SET_ENGINE_SCHED_FLAGS_IMMEDIATE ?
+		       GUC_SET_ENGINE_SCHED_IMM_MODE_ENABLE : GUC_SET_ENGINE_SCHED_IMM_MODE_DISABLE;
+	u32 g2h_len_dw = HOST2GUC_SET_ENGINE_SCHED_RESPONSE_MSG_LEN;
+	u32 request[HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_LEN] = {
+		FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
+		FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
+		FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SET_ENGINE_SCHED),
+		FIELD_PREP(HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_1_ENGINE_CLASS, class),
+		FIELD_PREP(HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_2_STATE, state),
+		FIELD_PREP(HOST2GUC_SET_ENGINE_SCHED_REQUEST_MSG_3_IMM_MODE, imm_mode),
+	};
+
+	GEM_BUG_ON(class > MAX_ENGINE_INSTANCE);
+
+	return guc_submission_send_busy_loop(guc, request, ARRAY_SIZE(request), g2h_len_dw, true);
+}
+
+int intel_guc_process_set_engine_sched_done(struct intel_guc *guc, const u32 *msg, u32 len)
+{
+	if (len != GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_LEN)
+		return -EPROTO;
+
+	if (FIELD_GET(GUC2HOST_SET_ENGINE_SCHED_DONE_MSG_0_MBZ, msg[0] != 0))
+		return -EPROTO;
+
+	decr_outstanding_submission_g2h(guc);
+
+	return 0;
+}
+
 static void __guc_context_sched_enable(struct intel_guc *guc,
 				       struct intel_context *ce)
 {

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h

@@ -54,6 +54,12 @@ static inline bool intel_guc_submission_is_used(const struct intel_guc *guc)
 	return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc);
 }
 
+int intel_guc_set_engine_sched(struct intel_guc *guc, u32 class, u32 flags);
+#define SET_ENGINE_SCHED_FLAGS_ENABLE		BIT(0)
+#define SET_ENGINE_SCHED_FLAGS_IMMEDIATE	BIT(1)
+
+int intel_guc_process_set_engine_sched_done(struct intel_guc *guc, const u32 *msg, u32 len);
+
 static inline u16 intel_guc_submission_ids_in_use(struct intel_guc *guc)
 {
 	return guc->submission_state.guc_ids_in_use;

drivers/gpu/drm/i915/i915_driver.c

@@ -779,8 +779,6 @@ static void i915_virtualization_probe(struct drm_i915_private *i915)
  */
 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
-	const struct intel_device_info *match_info =
-		(struct intel_device_info *)ent->driver_data;
 	struct drm_i915_private *i915;
 	int ret;
 
@@ -837,7 +835,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	if (ret)
 		goto out_cleanup_modeset2;
 
-	intel_pxp_init(i915);
+	ret = intel_pxp_init(i915);
+	if (ret != -ENODEV)
+		drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
 
 	ret = intel_display_driver_probe(i915);
 	if (ret)

drivers/gpu/drm/i915/i915_getparam.c

@@ -109,7 +109,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
 			return value;
 		break;
 	case I915_PARAM_PXP_STATUS:
-		value = intel_pxp_get_readiness_status(i915->pxp);
+		value = intel_pxp_get_readiness_status(i915->pxp, 0);
 		if (value < 0)
 			return value;
 		break;

drivers/gpu/drm/i915/i915_scatterlist.h

@@ -156,10 +156,9 @@ bool i915_sg_trim(struct sg_table *orig_st);
  * struct i915_refct_sgt_ops - Operations structure for struct i915_refct_sgt
  */
 struct i915_refct_sgt_ops {
-	/**
-	 * release() - Free the memory of the struct i915_refct_sgt
-	 * @ref: struct kref that is embedded in the struct i915_refct_sgt
-	 */
+        /**
+         * @release: Free the memory of the struct i915_refct_sgt
+         */
 	void (*release)(struct kref *ref);
 };