Merge V0.2 into main

phoeniX-Digital-Design · Dec 30, 2023 · da417dc · da417dc
2 parents cb57918 + 7bc42c0
commit da417dc
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diff --git a/AssembleX.py → AssembleX_V1.0.py b/AssembleX.py → AssembleX_V1.0.py
@@ -1,10 +1,11 @@
 # ----------------------------------------------------------------
-# |                          AssembleX                           |
+# |                       AssembleX V0.1                         |
 # | ------------------------------------------------------------ |
 # | Custom-built RISC-V assembly code executant for phoeniX core |
 # |          By : Arvin Delavari - Faraz Ghoreishy               |
 # |   Iran University of Science and Technology - Summer 2023    |
 # ----------------------------------------------------------------
+
 import os
 import sys
 import glob
@@ -61,14 +62,14 @@
 # OS : cmd commands to execute Verilog simulations:
 os.system("iverilog -IModules -o phoeniX.vvp phoeniX_Testbench.v") 
 os.system("vvp phoeniX.vvp") 
-with open(testbench_file, 'w') as file:
-    for line in lines:
-        # Change testbench file
-        if line.startswith("\t`define FIRMWARE"):
-            print("Line found!")
-            # Remove firmware file address
-            modified_line = line.replace(line,'\t`define FIRMWARE\n')
-            file.write(modified_line)
-        else:
-            file.write(line)
+# with open(testbench_file, 'w') as file:
+#     for line in lines:
+#         # Change testbench file
+#         if line.startswith("\t`define FIRMWARE"):
+#             print("Line found!")
+#             # Remove firmware file address
+#             modified_line = line.replace(line,'\t`define FIRMWARE\n')
+#             file.write(modified_line)
+#         else:
+#             file.write(line)
 os.system("gtkwave phoeniX.gtkw") 
diff --git a/...CV_Original_Documents/RISCV_greencard.pdf → ...iginal_Documents/RISCV_Reference_Card.pdf b/...CV_Original_Documents/RISCV_greencard.pdf → ...iginal_Documents/RISCV_Reference_Card.pdf
diff --git a/Documents/RISCV_Original_Documents/riscv-privileged-20211203.pdf b/Documents/RISCV_Original_Documents/riscv-privileged-20211203.pdf
diff --git a/Documents/RISCV_Original_Documents/riscvcard.pdf b/Documents/RISCV_Original_Documents/riscvcard.pdf
diff --git a/...atform for Approximate Computing V0.1.pdf → ...atform for Approximate Computing V0.1.pdf b/...atform for Approximate Computing V0.1.pdf → ...atform for Approximate Computing V0.1.pdf
diff --git a/Documents/phoeniX_Documentation_V0.2/phoeniX_RISC-V_Core_V0.1.pdf b/Documents/phoeniX_Documentation_V0.2/phoeniX_RISC-V_Core_V0.1.pdf
diff --git a/Makefile b/Makefile
@@ -9,7 +9,7 @@ CORE_TESTBENCH = $(CORE_NAME)_Testbench.v
 TOOLCHAIN_PREFIX = riscv64-unknown-elf-
 
 MABI = ilp32
-MARCH = rv32i
+MARCH = rv32im
 
 CFLAGS = -mabi=$(MABI) -march=$(MARCH)
 CFLAG_LINKING = -Wl,--gc-sections
@@ -48,7 +48,7 @@ firmware.hex: start.elf firmware.elf
 
 firmware.elf: $(OBJECT_C) $(OBJECT_S)
 	$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) -o $(PROJECT_DIR)/syscalls.o $(FIRMWARE_DIR)/syscalls.c
-	$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) $(CFLAG_LINKING) -o $(PROJECT_DIR)/$(project)_firmware.elf $< $(PROJECT_DIR)/syscalls.o -T $(FIRMWARE_DIR)/riscv.ld -lstdc++
+	$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) $(CFLAG_LINKING) -o $(PROJECT_DIR)/$(project)_firmware.elf $^ $(PROJECT_DIR)/syscalls.o -T $(FIRMWARE_DIR)/riscv.ld -lstdc++
 	$(TOOLCHAIN_PREFIX)objdump -d $(PROJECT_DIR)/$(project)_firmware.elf > $(PROJECT_DIR)/$(project)_firmware.txt
 	$(TOOLCHAIN_PREFIX)objcopy -O verilog $(PROJECT_DIR)/$(project)_firmware.elf $(PROJECT_DIR)/firmware.tmp
 
@@ -57,10 +57,11 @@ start.elf:
 	$(TOOLCHAIN_PREFIX)objcopy -O verilog $(PROJECT_DIR)/$(project)_start.elf $(PROJECT_DIR)/start.tmp
 
 $(OBJECT_C): $(SOURCE_C)
-	@echo "Hello are you there?"
+	@echo "Compiling C files"
 	$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) -o $@ $<
 
 $(OBJECT_S): $(SOURCE_S)
+	@echo "Compiling ASM files"
 	$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) -o $@ $<
 
 %::