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Cleanup of some latent verible changes. #318

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Cleanup of some latent verible changes. #318

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7fb74ee
Cleanup of some latent verible changes.
MikeOpenHWGroup Jul 13, 2023
3e0bb60
Merge branch 'master' into cleanup-verible
MikeOpenHWGroup Aug 30, 2023
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6 changes: 3 additions & 3 deletions rtl/core-v-mcu/soc/soc_interconnect_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ module soc_interconnect_wrap
//Everything that is not routed to port 1 or 2 ends up in port 0 by default
localparam addr_map_rule_t [NR_RULES_L2_DEMUX-1:0] L2_DEMUX_RULES = '{
'{ idx: 1 , start_addr: `SOC_MEM_MAP_PRIVATE_BANK0_START_ADDR , end_addr: `SOC_MEM_MAP_PRIVATE_BANK1_END_ADDR} , //Both , bank0 and bank1 are in the same address block
'{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR} ,
'{ idx: 1 , start_addr: `SOC_MEM_MAP_BOOT_ROM_START_ADDR , end_addr: `SOC_MEM_MAP_BOOT_ROM_END_ADDR} ,
'{ idx: 1 , start_addr: `EFPGA_ASYNC_APB_START_ADDR , end_addr: `EFPGA_ASYNC_APB_END_ADDR},
'{ idx: 2 , start_addr: `SOC_MEM_MAP_TCDM_START_ADDR , end_addr: `SOC_MEM_MAP_TCDM_END_ADDR }
};
Expand All @@ -90,8 +90,8 @@ module soc_interconnect_wrap

localparam NR_RULES_AXI_CROSSBAR = 1;
localparam addr_map_rule_t [NR_RULES_AXI_CROSSBAR-1:0] AXI_CROSSBAR_RULES = '{
// '{ idx: 0, start_addr: `SOC_MEM_MAP_AXI_PLUG_START_ADDR, end_addr: `SOC_MEM_MAP_AXI_PLUG_END_ADDR},
'{ idx: 0, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}
// '{ idx: 0, start_addr: `SOC_MEM_MAP_AXI_PLUG_START_ADDR, end_addr: `SOC_MEM_MAP_AXI_PLUG_END_ADDR},
'{ idx: 0, start_addr: `SOC_MEM_MAP_PERIPHERALS_START_ADDR, end_addr: `SOC_MEM_MAP_PERIPHERALS_END_ADDR}
};

//For legacy reasons, the fc_data port can alias the address prefix 0x000 to 0x1c0. E.g. an access to 0x00001234 is
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