adding the copyright head comments in all the required files

openhwgroup · Jan 18, 2024 · 3b45f1e · 3b45f1e
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diff --git a/docs/doc-src/ip-blocks/apb_adv_timer.rst b/docs/doc-src/ip-blocks/apb_adv_timer.rst
@@ -3,7 +3,19 @@
    Copyright (c) 2024 CircuitSutra
 
    SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-.. _apb_adv_timer:
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_advanced_timer:
 
 APB Advanced Timer
 ==================

diff --git a/docs/doc-src/ip-blocks/apb_event_cntrl.rst b/docs/doc-src/ip-blocks/apb_event_cntrl.rst
@@ -1,3 +1,22 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_event_control:
+
 APB EVENT CONTROL
 ==================
 This APB peripheral device collects all the events which are

diff --git a/docs/doc-src/ip-blocks/apb_fll_if.rst b/docs/doc-src/ip-blocks/apb_fll_if.rst
@@ -1,3 +1,22 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_fll_if:
+
 **APB FLL:-**
 
 -  Core-V-MCU contains 3 FLLs. One FLL is meant for generating the clock

diff --git a/docs/doc-src/ip-blocks/apb_gpio.rst b/docs/doc-src/ip-blocks/apb_gpio.rst
@@ -1,37 +1,39 @@
-**Author’s Notes:** (this should not be part of the specifications):
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
 
--  In order to prepare this document. I have tried to understand the
-      system verilog code placed in git
-      https://github.com/openhwgroup/core-v-mcu/blob/master/rtl/apb_gpio/rtl/apb_gpio.sv
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
--  I have created this block diagram using the
-      https://lucid.app/lucidchart/df5461ff-e4f0-4f5c-a09b-7e8aeeed2a7f/edit?beaconFlowId=96B7DACD40CCA0A9&invitationId=inv_bdd3a7f7-544e-4611-bb61-4264601b3d64&page=0_0#
+.. Level 1
+   =======
 
--  The logic for OUT1, OUT2, OUT3, PIN1, PIN2, PIN3 registers are not
-      supported in the system-verilog code in the git hub.
+   Level 2
+   -------
 
--  The logic for the rising_edge and falling_edge interrupts is not
-      clear in the system verilog code as the RTL is not holding the
-      previous values of inputs.
+   Level 3
+   ~~~~~~~
 
--  The logic for the open drain for the gpio_out port is also not clear
-      for the open drain mode.
+   Level 4
+   ^^^^^^^
+.. _apb_gpio:
 
--  I have copied the register set from the kshitij’s document. Need to
-      check if we can make it better.
-
-**APB_GPIO**\ The General Purpose Input/Output (GPIO) IP block supports S/W access
+APB_GPIO
+========
+The General Purpose Input/Output (GPIO) IP block supports S/W access
 to read and write the values on selected I/O, and configuring selected
 I/O to generate interrupts.
 
-**Features**
+Features
+--------
 
 -  32-bit bits of user-selectable I/O.
 
 -  I/O can be configured for level type interrupts or edge triggered
       interrupts.
 
-**Theory of Operation**\ Block diagram of APB_GPIO peripheral:
+Theory of Operation
+^^^^^^^^^^^^^^^^^^^
+Block diagram of APB_GPIO peripheral:
 
 .. image:: apb_gpio_image.png
    :width: 5in

diff --git a/docs/doc-src/ip-blocks/apb_i2cs.rst b/docs/doc-src/ip-blocks/apb_i2cs.rst
@@ -1,3 +1,22 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_i2c_slave:
+
 **APB I2C SLAVE**
 =================
 

diff --git a/docs/doc-src/ip-blocks/apb_soc_ctrl.rst b/docs/doc-src/ip-blocks/apb_soc_ctrl.rst
@@ -1,4 +1,23 @@
 
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_soc_controller:
+
 **APB SoC controller**
 ======================
 

diff --git a/docs/doc-src/ip-blocks/apb_timer.rst b/docs/doc-src/ip-blocks/apb_timer.rst
@@ -1,3 +1,22 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _apb_timer:
+
 **APB Timer**
 =============
 

diff --git a/docs/doc-src/ip-blocks/udma_cam.rst b/docs/doc-src/ip-blocks/udma_cam.rst
@@ -1,5 +1,24 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _udma_cam:
+
 uDMA CAMERA
-==================
+===========
 A camera interface is a hardware block that interfaces with different
 image sensor interfaces and generates output that can be used for
 image processing.

diff --git a/docs/doc-src/ip-blocks/udma_sdio.rst b/docs/doc-src/ip-blocks/udma_sdio.rst
@@ -1,17 +1,39 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2024 CircuitSutra
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+.. _udma_sd_card_interface:
+
 UDMA SD CARD INTERFACE
+======================
 
 The SDIO (Secure digital I/O) card provides high speed data I/O with low
 power consumption for mobile electronic devices. Host devices supporting
 SDIO can connect the SD slot with I/O devices like Bluetooth, wireless,
 LAN, GPS Receiver, Digit Camera etc.
 
 SDIO INTERFACE BUS:
+-------------------
 
 .. udma_sdio_image:: udma_sdio_image8.png
    :width: 4.17708in
    :height: 2.51042in
 
 FEATURES:
+---------
 
 -  It has a clock, command and 4-bit data bus.
 
@@ -42,6 +64,7 @@ FEATURES:
    -  Response busy timeout
 
 THEORY OF OPERATION:
+^^^^^^^^^^^^^^^^^^^^
 
 Communication over the SD bus is based on command and data bit streams
 that are initiated by a start and terminated by a stop bit.
@@ -115,7 +138,7 @@ Data transfer to/from the SD memory card is done in blocks. Data blocks
 are succeeded by CRC bits.
 
 BLOCK DIAGRAM:
-
+^^^^^^^^^^^^^^
 .. udma_sdio_image:: udma_sdio_image6.png
    :width: 4.72292in
    :height: 5.44022in
@@ -130,6 +153,7 @@ Command module handles command interface and data module handles data
 transfer.
 
 SDIO TX/RX:
+^^^^^^^^^^^
 
 This module is responsible for sending and receiving command and data
 between host and device. It instantiates command and data modules.