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Hello, I use RISC-V as the driver CPU for NVDLA,and in order to adapt to the SOC corresponding to Large NVDLA, I used the compiler to generate the Loadable file corresponding to Lenet mini. Before generating the loadable file, I opened the SRAM enable function as follows: // setUseCVSRAMAllocate(true);
Then I executed the following command to generate the corresponding loadable file in Large mode: ./nvdla-sw/umd/out/apps/compiler/nvdla_compiler/nvdla_compiler --profile performance --configtarget nv_large --cprecision int8 --prototxt /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.prototxt --caffemodel /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.caffemodel --informat nchw --calibtable /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.int8.json
However, when executing the inference, the following error occurred:
Hello, I use RISC-V as the driver CPU for NVDLA,and in order to adapt to the SOC corresponding to Large NVDLA, I used the compiler to generate the Loadable file corresponding to Lenet mini. Before generating the loadable file, I opened the SRAM enable function as follows:
// setUseCVSRAMAllocate(true);
Then I executed the following command to generate the corresponding loadable file in Large mode:
./nvdla-sw/umd/out/apps/compiler/nvdla_compiler/nvdla_compiler --profile performance --configtarget nv_large --cprecision int8 --prototxt /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.prototxt --caffemodel /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.caffemodel --informat nchw --calibtable /home/yyx/riscv/document/nvdla_loadables/lenet-minist-caffe/lenet-minist.int8.json
However, when executing the inference, the following error occurred:
What could be the reason? Thanks
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