Pinned Loading

1. ucb-bar/chipyard ucb-bar/chipyard Public

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala 1.6k 650

2. eugene-tarassov/vivado-risc-v eugene-tarassov/vivado-risc-v Public

   Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

   Tcl 843 192