add changes required for successful Vivado 2017.4 synthesis (nv_small…

… only)
nvdla · Jun 14, 2018 · 1428251 · 1428251
1 parent e18de04
commit 1428251
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Showing 20 changed files with 106 additions and 53 deletions.
diff --git a/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v b/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v
@@ -407,7 +407,7 @@ wire           dma_rd_req_vld;
 //:     wire   [${M}-1:0] dma_rd_rsp_mask;
 //: );
 //: foreach my $k (0..$M-1) {
-//: print qq( reg    [${atmm}-1:0] dma_rsp_data_p${k}; \n);
+//: print qq(wire   [${atmm}-1:0] dma_rsp_data_p${k}; \n);
 //: }
 wire           dma_rd_rsp_rdy;
 wire           dma_rd_rsp_vld;

diff --git a/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v b/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v
@@ -206,8 +206,8 @@ input         status2dma_fsm_switch;
 //:          output               img2sbuf_p${i}_wr_en  ;  
 //:          output [7:0]         img2sbuf_p${i}_wr_addr;
 //:          output [${atmm}-1:0] img2sbuf_p${i}_wr_data;
-//:          output reg           img2sbuf_p${i}_rd_en;
-//:          output reg [7:0]     img2sbuf_p${i}_rd_addr;
+//:          output               img2sbuf_p${i}_rd_en;
+//:          output [7:0]         img2sbuf_p${i}_rd_addr;
 //:          input  [${atmm}-1:0] img2sbuf_p${i}_rd_data;
 //:     );
 //: }

diff --git a/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v b/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v
@@ -259,8 +259,8 @@ reg            dbg_src_rd_ptr;
 reg            dbg_src_wr_ptr;
 reg     [31:0] dbg_wmb_kernel_bits;
 reg     [31:0] dbg_wt_kernel_bytes;
-reg      [3:0] dma_req_size;
-reg      [2:0] dma_req_size_out;
+wire     [3:0] dma_req_size;
+wire     [2:0] dma_req_size_out;
 
 //: my $mask = NVDLA_CDMA_MEM_MASK_BIT;
 //: my $atmm = (NVDLA_MEMORY_ATOMIC_SIZE * NVDLA_BPE);
@@ -273,15 +273,15 @@ reg      [2:0] dma_req_size_out;
 //:     );
 //: foreach my $i(0..$mask-1) {
 //:     print qq(
-//:         reg    [${atmm}-1:0] dma_rsp_data_p${i};
+//:         wire   [${atmm}-1:0] dma_rsp_data_p${i};
 //:     );
 //: }
 wire   [NVDLA_CDMA_DMAIF_BW-1:0] wt_cbuf_wr_data_ori_w;
 wire   [NVDLA_CDMA_DMAIF_BW-1:0] wt_cbuf_wr_data_w;
 reg    [NVDLA_CDMA_DMAIF_BW-1:0] cdma2buf_wt_wr_data;
 wire   [NVDLA_CDMA_DMAIF_BW-1:0] wmb_cbuf_wr_data_w;
 wire   [NVDLA_CDMA_DMAIF_BW-1:0] cdma2buf_wt_wr_data_w;
-reg      [3:0] dma_rsp_size;
+wire     [3:0] dma_rsp_size;
 reg      [3:0] dma_rsp_size_cnt;
 wire     [31:0] dp2reg_wt_rd_latency=32'd0;
 reg     [31:0] dp2reg_wt_rd_stall;
@@ -301,8 +301,8 @@ reg     [10:0] ltc_1_cnt_mod;
 reg     [10:0] ltc_1_cnt_new;
 reg     [10:0] ltc_1_cnt_nxt;
 reg      [8:0] ltc_1_cnt_cur;
-reg            ltc_1_dec;
-reg            ltc_1_inc;
+wire           ltc_1_dec;
+wire           ltc_1_inc;
 reg            ltc_2_adv;
 reg     [33:0] ltc_2_cnt_dec;
 reg     [33:0] ltc_2_cnt_ext;
@@ -622,7 +622,7 @@ wire           wt_local_data_vld_w;
 //:     wire    [64-${atmbw}-1:0] wt_req_addr_w;
 //:     reg     [64-${atmbw}-1:0] wt_req_addr_d2;
 //:     reg     [64-${atmbw}-1:0] wt_req_addr_d3;
-//:     reg     [64-${atmbw}-1:0] dma_req_addr;
+//:     wire    [64-${atmbw}-1:0] dma_req_addr;
 //:     wire    [64-${atmbw}-1-3:0] wt_req_addr_inc;
 //:     wire    [64-${atmbw}-1:0] wmb_req_addr_w;
 //:     reg     [64-${atmbw}-1:0] wmb_req_addr_d2;

diff --git a/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v b/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v
@@ -94,14 +94,14 @@ reg           lut2intp_pvld;
 //: my $k = NVDLA_CDP_THROUGHPUT;
 //: foreach my $m  (0..$k-1) {
 //:     print qq(
-//:         reg    [31:0] lut2intp_X_data_${m}0;
-//:         reg    [16:0] lut2intp_X_data_${m}0_17b;
-//:         reg    [31:0] lut2intp_X_data_${m}1;
-//:         reg    [19:0] lut2intp_X_info_${m};
+//:         wire   [31:0] lut2intp_X_data_${m}0;
+//:         wire   [16:0] lut2intp_X_data_${m}0_17b;
+//:         wire   [31:0] lut2intp_X_data_${m}1;
+//:         wire   [19:0] lut2intp_X_info_${m};
 //:     );
 //: }
-reg     [NVDLA_CDP_THROUGHPUT-1:0] lut2intp_X_sel;
-reg     [NVDLA_CDP_THROUGHPUT-1:0] lut2intp_Y_sel;
+wire    [NVDLA_CDP_THROUGHPUT-1:0] lut2intp_X_sel;
+wire    [NVDLA_CDP_THROUGHPUT-1:0] lut2intp_Y_sel;
 reg     [NVDLA_CDP_THROUGHPUT-1:0] lutX_sel;
 reg     [NVDLA_CDP_THROUGHPUT-1:0] lutY_sel;
 //: my $k = NVDLA_CDP_THROUGHPUT;

diff --git a/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v b/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v
@@ -88,13 +88,13 @@ reg      [3:0] beat_cnt;
 reg            cdp2cvif_rd_cdt_lat_fifo_pop;
 #endif
 reg            cdp2mcif_rd_cdt_lat_fifo_pop;
-reg     [NVDLA_CDP_THROUGHPUT*NVDLA_BPE+22:0] cdp_rdma2dp_pd;
+wire    [NVDLA_CDP_THROUGHPUT*NVDLA_BPE+22:0] cdp_rdma2dp_pd;
 //reg            cdp_rdma2dp_valid_f;
-reg            dp2reg_done_flag;
+wire           dp2reg_done_flag;
 reg     [NVDLA_CDP_THROUGHPUT*NVDLA_BPE-1:0] dp_data;
 wire           dp_rdy;
 reg            dp_vld;
-reg            eg2ig_done_flag;
+wire           eg2ig_done_flag;
 reg      [NVDLA_CDP_THROUGHPUT-1:0] invalid_flag;
 reg            is_last_c;
 reg            is_last_h;

diff --git a/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v b/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v
@@ -95,7 +95,7 @@ reg    [31:0] mon_gap_between_layers;
 reg           mon_layer_end_flg;
 reg           mon_op_en_dly;
 reg           mon_size_of_32x1_in_first_block_in_width_c;
-reg    [10:0] number_of_total_trans_in_width;
+wire   [10:0] number_of_total_trans_in_width;
 reg     [2:0] req_size;
 reg     [2:0] size_of_32x1_in_first_block_in_width;
 reg           stl_adv;

diff --git a/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v b/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v
@@ -95,7 +95,7 @@ reg            cv_dma_wr_rsp_complete;
 reg            cv_pending;
 reg            dat_en;
 reg     [63:0] dma_req_addr;
-reg            dma_wr_rsp_complete;
+wire           dma_wr_rsp_complete;
 reg     [31:0] dp2reg_d0_perf_write_stall;
 reg     [31:0] dp2reg_d1_perf_write_stall;
 //: my $jx = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_BPE;

diff --git a/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v b/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v
@@ -95,15 +95,15 @@ input   [CMAC_ATOMK_HALF-1:0] in_wt_sel;
 //: reg  [CMAC_BPE*CMAC_ATOMC-1:0]  dat_actv_data_reg${i};
 //: )
 //: }
-reg    [CMAC_BPE*CMAC_ATOMC-1:0]    dat_pre_data_w;
+wire   [CMAC_BPE*CMAC_ATOMC-1:0]    dat_pre_data_w;
 wire   [CMAC_ATOMC-1:0]             dat_pre_mask_w;
 reg    [CMAC_ATOMC-1:0]             dat_pre_nz_w;
 reg                                 dat_pre_stripe_end;
 reg                                 dat_pre_stripe_st;
 reg    [CMAC_BPE*CMAC_ATOMC-1:0]    wt_pre_data;
-reg    [CMAC_BPE*CMAC_ATOMC-1:0]    wt_pre_data_w;
+wire   [CMAC_BPE*CMAC_ATOMC-1:0]    wt_pre_data_w;
 reg    [CMAC_ATOMC-1:0]             wt_pre_mask;
-reg    [CMAC_ATOMC-1:0]             wt_pre_mask_w;
+wire   [CMAC_ATOMC-1:0]             wt_pre_mask_w;
 reg    [CMAC_ATOMC-1:0]             wt_pre_nz_w;
 
 

diff --git a/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v b/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v
@@ -25,8 +25,8 @@ input        reg2dp_conv_mode;
 input        reg2dp_op_en;
 output       cfg_is_wg;
 output       cfg_reg_en;
-reg          cfg_is_wg_w;
-reg          cfg_reg_en_w;
+wire         cfg_is_wg_w;
+wire         cfg_reg_en_w;
 
 
 //: &eperl::flop(" -q  op_en_d1  -d \"reg2dp_op_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); 

diff --git a/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v b/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v
@@ -53,10 +53,10 @@ output                          dp2reg_done;
 output   [CMAC_ATOMK_HALF-1:0]  mac2accu_mask;
 output   [8:0]                  mac2accu_pd;
 output                          mac2accu_pvld;
-reg      [CMAC_ATOMK_HALF-1:0]  mac2accu_mask;
-reg      [8:0]                  mac2accu_pd;
-reg                             mac2accu_pvld;
-reg                             out_layer_done;
+wire     [CMAC_ATOMK_HALF-1:0]  mac2accu_mask;
+wire     [8:0]                  mac2accu_pd;
+wire                            mac2accu_pvld;
+wire                            out_layer_done;
 wire                            out_rt_done_d0;
 
 

diff --git a/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v b/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v
@@ -49,8 +49,8 @@ reg     [CSC_ATOMC*CSC_BPE-1:0] data_d1;
 reg     [CSC_ATOMC-1:0] mask_d1;
 //reg     [CSC_ATOMC-1:0] mask_d2_fp16_w;
 //reg     [CSC_ATOMC-1:0] mask_d2_int16_w;
-reg     [CSC_ATOMC-1:0] mask_d2_int8_w;
-reg     [CSC_ATOMC-1:0] mask_d2_w;
+wire    [CSC_ATOMC-1:0] mask_d2_int8_w;
+wire    [CSC_ATOMC-1:0] mask_d2_w;
 reg     [CSC_ATOMC-1:0] mask_d3;
 reg      [CSC_ATOMK-1:0] sel_d1;
 reg      [CSC_ATOMK-1:0] sel_d2;
@@ -73,7 +73,7 @@ reg             valid_d3;
 //:     }
 //:     my $k = $j - 1;
 //:     my $series_no = sprintf("%02d", $i);
-//:     print qq(reg       [${k}:0] vec_sum_${series_no};\n);
+//:     print qq(wire      [${k}:0] vec_sum_${series_no};\n);
 //:     print qq(reg       [${k}:0] vec_sum_${series_no}_d1;\n);
 //: }
 

diff --git a/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v b/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v
@@ -197,16 +197,16 @@ reg       [1:0] dat_req_sub_w_d2;
 reg             dat_req_sub_w_st_d1;
 reg             dat_req_sub_w_st_d2;
 reg             dat_req_valid_d1;
-reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l0_sft;
+wire   [CBUF_ENTRY_BITS-1:0] dat_rsp_l0_sft;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l0_sft_d1;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l0_sft_d2;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l0_sft_d3;
-reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l1_sft;
+wire   [CBUF_ENTRY_BITS-1:0] dat_rsp_l1_sft;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l1_sft_d2;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l1_sft_d3;
-reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l2_sft;
+wire   [CBUF_ENTRY_BITS-1:0] dat_rsp_l2_sft;
 reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l2_sft_d3;
-reg    [CBUF_ENTRY_BITS-1:0] dat_rsp_l3_sft;
+wire   [CBUF_ENTRY_BITS-1:0] dat_rsp_l3_sft;
 reg      [26:0] dat_rsp_pd_d1;
 reg      [26:0] dat_rsp_pd_d2;
 reg      [26:0] dat_rsp_pd_d3;

diff --git a/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v b/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v
@@ -130,7 +130,7 @@ reg     [4:0] dat_pkg_h_offset;
 reg           dat_pkg_layer_end;
 reg     [6:0] dat_pkg_stripe_length;
 reg     [4:0] dat_pkg_w_offset;
-reg    [30:0] dat_pop_pd;
+wire   [30:0] dat_pop_pd;
 reg     [6:0] dat_stripe_length;
 reg     [6:0] dat_stripe_size;
 reg     [5:0] data_batch;
@@ -186,7 +186,7 @@ reg     [2:0] wt_pkg_cur_sub_h;
 reg     [6:0] wt_pkg_kernel_size;
 reg     [6:0] wt_pkg_weight_size;
 reg           wt_pkg_wt_release;
-reg    [17:0] wt_pop_pd;
+wire   [17:0] wt_pop_pd;
 reg           wt_pop_ready_d1;
 wire    [7:0] c_fetch_size;
 wire          cbuf_ready;

diff --git a/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v b/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v
@@ -65,9 +65,9 @@ reg     [12:0] line_cnt;
 reg            op_en_d1;
 reg     [4:0]  pos_c;
 reg     [4:0]  sdp2pdp_c_cnt;
-reg            sdp2pdp_en_sync;
+wire           sdp2pdp_en_sync;
 reg     [12:0] sdp2pdp_height_cnt;
-reg    [NVDLA_PDP_ONFLY_INPUT_BW-1:0] sdp2pdp_pd_use;
+wire    [NVDLA_PDP_ONFLY_INPUT_BW-1:0] sdp2pdp_pd_use;
 //: my $atomicm = NVDLA_MEMORY_ATOMIC_SIZE;
 //: my $k = int( log($atomicm)/log(2) );
 //: print "reg      [12-${k}:0] sdp2pdp_surf_cnt; \n";

diff --git a/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v b/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v
@@ -71,20 +71,20 @@ input [31:0] pwrbus_ram_pd;
 
 reg     [13:0] beat_cnt;
 wire           dma_rd_rsp_rdy;
-reg            dp2reg_done_flag;
+wire            dp2reg_done_flag;
 reg     [NVDLA_PDP_BWPE*NVDLA_PDP_THROUGHPUT-1:0] dp_data;
 wire           dp_rdy;
 reg            dp_vld;
-reg            eg2ig_done_flag;
+wire            eg2ig_done_flag;
 reg      [5:0] fifo_sel_cnt;
 reg            is_cube_end;
 reg            is_line_end;
 reg            is_split_end;
 reg            is_surf_end;
 reg            pdp2cvif_rd_cdt_lat_fifo_pop;
 reg            pdp2mcif_rd_cdt_lat_fifo_pop;
-reg     [NVDLA_PDP_BWPE*NVDLA_PDP_THROUGHPUT+11:0] pdp_rdma2dp_pd;
-reg            rdma2wdma_done_flag;
+wire    [NVDLA_PDP_BWPE*NVDLA_PDP_THROUGHPUT+11:0] pdp_rdma2dp_pd;
+wire            rdma2wdma_done_flag;
 reg      [3:0] tran_cnt;
 reg     [13:0] width_cnt;
 wire [NVDLA_PDP_MEM_RD_RSP-1:0] cv_dma_rd_rsp_pd;

diff --git a/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v b/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v
@@ -103,7 +103,7 @@ reg           mon_base_addr_width_c;
 reg    [31:0] mon_gap_between_layers;
 reg           mon_layer_end_flg;
 reg           mon_op_en_dly;
-reg    [14:0] number_of_byte_in_c;
+wire   [14:0] number_of_byte_in_c;
 reg           op_process;
 reg    [31:0] pdp_rd_stall_count;
 reg    [12:0] req_size;

diff --git a/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v b/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v
@@ -46,7 +46,7 @@ output        alu_op_prdy;
 output        alu_out_pvld;
 wire   [32:0] alu_sum;
 reg    [32:0] alu_dout;
-reg           mon_sum_c;
+wire          mon_sum_c;
 wire   [32:0] alu_data_ext;
 wire   [32:0] alu_data_final;
 wire   [31:0] alu_data_reg;

diff --git a/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v b/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v
@@ -87,7 +87,7 @@ wire           is_batch_end;
 reg     [12:0] count_h;
 reg     [12:0] count_w;
 reg     [13-AM_AW:0] count_c;
-reg            is_last_beat;
+wire           is_last_beat;
 wire           is_cube_end;
 wire           is_last_c;
 wire           is_last_h;
@@ -131,7 +131,7 @@ reg            out_vld_1bpe;
 reg            out_vld_2bpe;
 wire           out_accept;
 wire           out_rdy;
-reg            out_vld;
+wire           out_vld;
 wire   [AM_DW2:0] out_pd;
 
 

diff --git a/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v b/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v
@@ -178,10 +178,10 @@ wire           in_dat_accept;
 wire           in_dat_rdy;
 wire           is_last_beat;
 reg     [13:0] beat_count;
-reg            dfifo0_wr_en;
-reg            dfifo1_wr_en;
-reg            dfifo2_wr_en;
-reg            dfifo3_wr_en;
+wire           dfifo0_wr_en;
+wire           dfifo1_wr_en;
+wire           dfifo2_wr_en;
+wire           dfifo3_wr_en;
 wire   [AM_DW-1:0] dfifo0_wr_pd;
 wire           dfifo0_wr_prdy;
 wire           dfifo0_wr_pvld;

diff --git a/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v b/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v
@@ -0,0 +1,53 @@
+
+module nv_ram_rwsp_8x65 ( 
+		clk,
+		ra,
+		re,
+		ore,
+		dout,
+		wa,
+		we,
+		di,
+		pwrbus_ram_pd
+);
+
+parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0;
+
+// port list
+input			clk;
+input	[2:0]	ra;
+input			re;
+input			ore;
+output	[64:0]	dout;
+input	[2:0]	wa;
+input			we;
+input	[64:0]	di;
+input	[31:0]	pwrbus_ram_pd;
+
+//reg and wire list
+reg		[2:0]	ra_d;
+wire	[64:0]	dout;
+reg		[64:0]	M	[7:0];
+
+always @( posedge clk ) begin
+    if (we)
+       M[wa] <= di;
+end
+
+always @( posedge clk ) begin
+    if (re) 
+       ra_d <= ra;
+end
+
+wire	[64:0]	dout_ram = M[ra_d];
+
+reg		[64:0]	dout_r;
+always @( posedge clk ) begin
+   if (ore)
+       dout_r <= dout_ram;
+end
+
+assign dout = dout_r;
+
+
+endmodule