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nrf_wifi: Cleanup the RPU interface files
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Partially cleanup the RPU and FW interface files by removing unncessary
defines and structs.

Fixes: SHEL-2904

Signed-off-by: Sachin D Kulkarni <[email protected]>
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@sachinthegreen
sachinthegreen committed Aug 6, 2024
1 parent 51fc239 commit 117c95d
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Showing 2 changed files with 22 additions and 175 deletions.
19 changes: 0 additions & 19 deletions nrf_wifi/fw_if/umac_if/inc/fw/host_rpu_sys_if.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1491,25 +1491,6 @@ struct nrf_wifi_event_rftest {
struct rpu_evnt_rftest_info rf_test_info;
} __NRF_WIFI_PKD;

/**
* @brief This structure represents the power data event generated in response to
* the NRF_WIFI_CMD_PWR command.
*
* The NRF_WIFI_CMD_PWR command is used to retrieve power-related data or measurements
* from the radio hardware.
*
*/
struct nrf_wifi_event_pwr_data {
/** UMAC header, @ref nrf_wifi_sys_head */
struct nrf_wifi_sys_head sys_head;
/** Power monitor command status info */
signed int mon_status;
/** Data */
signed int data_type;
/** Data that host may want to read from Power IP */
struct nrf_wifi_rpu_pwr_data data;
} __NRF_WIFI_PKD;

/**
* @brief This structure is a comprehensive combination of all the firmware statistics
* that the RPU (Radio Processing Unit) can provide.
Expand Down
178 changes: 22 additions & 156 deletions nrf_wifi/hw_if/hal/inc/fw/rpu_if.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
#define __RPU_IF_H__
#include "pack_def.h"

#define RPU_ADDR_SPI_START 0x00000000
#define RPU_ADDR_GRAM_START 0xB7000000
#define RPU_ADDR_GRAM_END 0xB70101FF
#define RPU_ADDR_SBUS_START 0xA4000000
Expand Down Expand Up @@ -71,127 +70,53 @@ struct rpu_mcu_boot_vectors {
#define RPU_ADDR_MASK_OFFSET 0x00FFFFFF
#define RPU_ADDR_MASK_BEV_OFFSET 0x000FFFFF

/* Register locations from the Echo520 TRM */
#define RPU_REG_INT_FROM_RPU_CTRL 0xA4000400 /* 8.1.1 */
#define RPU_REG_INT_FROM_RPU_CTRL 0xA4000400
#define RPU_REG_BIT_INT_FROM_RPU_CTRL 17

#define RPU_REG_INT_TO_MCU_CTRL 0xA4000480 /* 8.3.7 */
#define RPU_REG_INT_TO_MCU_CTRL 0xA4000480

#define RPU_REG_INT_FROM_MCU_ACK 0xA4000488 /* 8.3.9 */
#define RPU_REG_INT_FROM_MCU_ACK 0xA4000488
#define RPU_REG_BIT_INT_FROM_MCU_ACK 31

#define RPU_REG_INT_FROM_MCU_CTRL 0xA4000494 /* 8.3.12 */
#define RPU_REG_INT_FROM_MCU_CTRL 0xA4000494
#define RPU_REG_BIT_INT_FROM_MCU_CTRL 31

#define RPU_REG_UCC_SLEEP_CTRL_DATA_0 0xA4002C2C /* 9.1.11 */
#define RPU_REG_UCC_SLEEP_CTRL_DATA_1 0xA4002C30 /* 9.1.12 */

#define RPU_REG_MIPS_MCU_CONTROL 0xA4000000 /* 13.1.1 */
#define RPU_REG_BIT_MIPS_MCU_LATCH_SOFT_RESET 1
#define RPU_REG_MIPS_MCU2_CONTROL 0xA4000100 /* 13.1.1 */
#define RPU_REG_UCC_SLEEP_CTRL_DATA_0 0xA4002C2C
#define RPU_REG_UCC_SLEEP_CTRL_DATA_1 0xA4002C30
#define RPU_REG_MIPS_MCU_CONTROL 0xA4000000
#define RPU_REG_MIPS_MCU2_CONTROL 0xA4000100

#define RPU_REG_MIPS_MCU_UCCP_INT_STATUS 0xA4000004
#define RPU_REG_BIT_MIPS_UCCP_INT_STATUS 0
#define RPU_REG_BIT_MIPS_WATCHDOG_INT_STATUS 1

#define RPU_REG_MIPS_MCU_TIMER_CONTROL 0xA4000048
#define RPU_REG_MIPS_MCU_TIMER 0xA400004C /* 24 bit timer@core clock ticks*/
#define RPU_REG_MIPS_MCU_TIMER_RESET_VAL 0xFFFFFF

#define RPU_REG_MIPS_MCU_UCCP_INT_CLEAR 0xA400000C
#define RPU_REG_BIT_MIPS_UCCP_INT_CLEAR 0
#define RPU_REG_BIT_MIPS_WATCHDOG_INT_CLEAR 1

#define RPU_REG_MIPS_MCU_SYS_CORE_MEM_CTRL 0xA4000030 /* 13.1.10 */
#define RPU_REG_MIPS_MCU_SYS_CORE_MEM_WDATA 0xA4000034 /* 13.1.11 */
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_0 0xA4000050 /* 13.1.15 */
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_1 0xA4000054 /* 13.1.16 */
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_2 0xA4000058 /* 13.1.17 */
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_3 0xA400005C /* 13.1.18 */

#define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_CTRL 0xA4000130 /* 13.1.10 */
#define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_WDATA 0xA4000134 /* 13.1.11 */
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_0 0xA4000150 /* 13.1.15 */
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_1 0xA4000154 /* 13.1.16 */
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_2 0xA4000158 /* 13.1.17 */
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_3 0xA400015C /* 13.1.18 */

#define RPU_REG_MCP_SYS_CSTRCTRL 0xA4001200
#define RPU_REG_MCP_SYS_CSTRDAT32 0xA4001218

#define RPU_REG_MCP2_SYS_CSTRCTRL 0xA4003200
#define RPU_REG_MCP2_SYS_CSTRDAT32 0xA4003218

#define RPU_REG_MCP3_SYS_CSTRCTRL 0xA4004200
#define RPU_REG_MCP3_SYS_CSTRDAT32 0xA4004218

#ifdef RPU_RF_C0_SUPPORT
#define PWR_CTRL1_SYSDEF 0xA4019000
#define PWR_COUNTERSTART_SYSDEF 0xA40190A0
#define PWR_COUNTERCYCLES_SYSDEF 0xA40190A4
#define PWR_COUNTERSTATUS0_SYSDEF 0xA40190B0
#define PWR_COUNTERSTATUS1_SYSDEF 0xA40190B4
#define PWR_COUNTERSTATUS2_SYSDEF 0xA40190B8
#define PWR_COUNTERSTATUS3_SYSDEF 0xA40190BC
#define WL_PWR_MON_SYSDEF 0xA4009310
#define WL_PWR_AUX_SYSDEF 0xA4009314
#define WL_PWR_VMON_CTRL_SYSDEF 0xA4009330
#define WL_PWR_VMON_DATA_SYSDEF 0xA4009334
#define WLAFE_WL_BBPLLEN_SYSDEF 0xA400B004
#define WLAFE_RG_BBPLL_CLK_01_SYSDEF 0xA400B050
#define WLAFE_RG_AFE_LDOCTRL_SYSDEF 0xA400B0F0

#define PWR_BREAKTIMER90_SYSDEF 0xA4019190
#define PWR_BREAKCOND2_SYSDEF 0xA4019094
#define PWR_BREAK3_SYSDEF 0xA4019080
#define PWR_BREAKCOND3_SYSDEF 0xA4019098
#define PWR_BREAK5_SYSDEF 0xA4019088

#else /* RPU_RF_C0_SUPPORT */

#define RPU_REG_RFCTL_UCC_RF_CTRL_CONFIG_00 0xA401C200
#define RPU_REG_RFCTL_UCC_RF_CTRL_CONFIG_01 0xA401C204
#define RPU_REG_RFCTL_UCC_RF_CTRL_CONFIG_02 0xA401C208
#define RPU_REG_RFCTL_UCC_RF_CTRL_CONFIG_04 0xA401C210
#define RPU_REG_RFCTL_UCC_RF_CTRL_CONFIG_16 0xA401C260
#define RPU_REG_RFCTL_SPI_CMD_DATA_TABLE_0 0xA401C300
#define RPU_REG_RFCTL_SPI_CMD_DATA_TABLE_1 0xA401C304
#define RPU_REG_RFCTL_SPI_CMD_DATA_TABLE_2 0xA401C308
#define RPU_REG_RFCTL_SPI_READ_DATA_TABLE_0 0xA401C380

#define PWR_CTRL1_SYSDEF 0x1040
#define PWR_COUNTERSTART_SYSDEF 0x1158
#define PWR_COUNTERCYCLES_SYSDEF 0x1159
#define PWR_COUNTERSTATUS0_SYSDEF 0x115C
#define PWR_COUNTERSTATUS1_SYSDEF 0x115D
#define PWR_COUNTERSTATUS2_SYSDEF 0x115E
#define PWR_COUNTERSTATUS3_SYSDEF 0x115F
#define WL_PWR_MON_SYSDEF 0x0144
#define WL_PWR_AUX_SYSDEF 0x0145

#define PWR_BREAKTIMER90_SYSDEF 0x1264
#define PWR_BREAKCOND2_SYSDEF 0x1155
#define PWR_BREAK3_SYSDEF 0x1150
#define PWR_BREAKCOND3_SYSDEF 0x1156
#define PWR_BREAK5_SYSDEF 0x1152

#define SPI_PAGESELECT 0x007C
#define SPI_DIGREFCLOCKCTRL 0x007D
#endif /* !RPU_RF_C0_SUPPORT */

#define RPU_REG_BIT_HARDRST_CTRL 8
#define RPU_REG_BIT_PS_CTRL 0
#define RPU_REG_MIPS_MCU_SYS_CORE_MEM_CTRL 0xA4000030
#define RPU_REG_MIPS_MCU_SYS_CORE_MEM_WDATA 0xA4000034
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_0 0xA4000050
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_1 0xA4000054
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_2 0xA4000058
#define RPU_REG_MIPS_MCU_BOOT_EXCP_INSTR_3 0xA400005C

#define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_CTRL 0xA4000130
#define RPU_REG_MIPS_MCU2_SYS_CORE_MEM_WDATA 0xA4000134
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_0 0xA4000150
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_1 0xA4000154
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_2 0xA4000158
#define RPU_REG_MIPS_MCU2_BOOT_EXCP_INSTR_3 0xA400015C

#define RPU_REG_BIT_PS_STATE 1
#define RPU_REG_BIT_READY_STATE 2

#define RPU_MEM_RX_CMD_BASE 0xB7000D58

#define RPU_MEM_HPQ_INFO 0xB0000024
#define RPU_MEM_TX_CMD_BASE 0xB00000B8
#define RPU_MEM_OTP_INFO 0xB000005C
#define RPU_MEM_OTP_FT_PROG_VERSION 0xB0004FD8
#define RPU_MEM_OTP_INFO_FLAGS 0xB0004FDC
#define RPU_MEM_LMAC_IF_INFO 0xB0004FE0
#define RPU_MEM_OTP_PACKAGE_TYPE 0xB0004FD4

#define RPU_MEM_PKT_BASE 0xB0005000
Expand All @@ -200,24 +125,9 @@ struct rpu_mcu_boot_vectors {
#define RPU_DATA_CMD_SIZE_MAX_TX 148
#define RPU_EVENT_COMMON_SIZE_MAX 128

/*Event pool*/
#define EVENT_POOL_NUM_ELEMS (7)
#define MAX_EVENT_POOL_LEN 1000

#define MAX_NUM_OF_RX_QUEUES 3

#define NRF_WIFI_RPU_PWR_DATA_TYPE_LFC_ERR 0
#define NRF_WIFI_RPU_PWR_DATA_TYPE_VBAT_MON 1
#define NRF_WIFI_RPU_PWR_DATA_TYPE_TEMP 2
#define NRF_WIFI_RPU_PWR_DATA_TYPE_ALL 3
#define NRF_WIFI_RPU_PWR_DATA_TYPE_MAX 4

#ifndef RPU_RF_C0_SUPPORT
#define NRF_WIFI_RPU_RF_CLK_TYPE_20 0
#define NRF_WIFI_RPU_RF_CLK_TYPE_40 1
#define NRF_WIFI_RPU_RF_CLK_TYPE_MAX 2
#endif /* RPU_RF_C0_SUPPORT */

#define RPU_PKTRAM_SIZE (RPU_ADDR_PKTRAM_END - RPU_MEM_PKT_BASE + 1)

#ifdef CONFIG_NRF700X_RADIO_TEST
Expand All @@ -242,22 +152,13 @@ struct rpu_mcu_boot_vectors {
#define PRODTEST_TRIM12 44
#define PRODTEST_TRIM13 45
#define PRODTEST_TRIM14 46
#define PRODCTRL_DISABLE5GHZ 47
#define INFO_PART 48
#define INFO_VARIANT 49
#define INFO_UUID 52
#define QSPI_KEY 68
#define MAC0_ADDR 72
#define MAC1_ADDR 74
#define CALIB_XO 76
#define CALIB_PDADJM7 77
#define CALIB_PDADJM0 78
#define CALIB_PWR2G 79
#define CALIB_PWR5GM7 80
#define CALIB_PWR5GM0 81
#define CALIB_RXGNOFF 82
#define CALIB_TXPOWBACKOFFT 83
#define CALIB_TXPOWBACKOFFV 84
#define REGION_DEFAULTS 85
#define PRODRETEST_PROGVERSION 86
#define PRODRETEST_TRIM0 87
Expand All @@ -281,47 +182,15 @@ struct rpu_mcu_boot_vectors {

/* Size of OTP fields in bytes */
#define OTP_SZ_CALIB_XO 1
#define OTP_SZ_CALIB_PDADJM7 4
#define OTP_SZ_CALIB_PDADJM0 4
#define OTP_SZ_CALIB_PWR2G 1
#define OTP_SZ_CALIB_PWR2GM0M7 2
#define OTP_SZ_CALIB_PWR5GM7 3
#define OTP_SZ_CALIB_PWR5GM0 3
#define OTP_SZ_CALIB_RXGNOFF 4
#define OTP_SZ_CALIB_TXP_BOFF_2GH 1
#define OTP_SZ_CALIB_TXP_BOFF_2GL 1
#define OTP_SZ_CALIB_TXP_BOFF_5GH 1
#define OTP_SZ_CALIB_TXP_BOFF_5GL 1
#define OTP_SZ_CALIB_TXP_BOFF_V 4

/* Offsets of OTP calib values in the calib field */
#define OTP_OFF_CALIB_XO 0
#define OTP_OFF_CALIB_PDADJM7 4
#define OTP_OFF_CALIB_PDADJM0 8
#define OTP_OFF_CALIB_PWR2G 12
#define OTP_OFF_CALIB_PWR2GM0M7 13
#define OTP_OFF_CALIB_PWR5GM7 16
#define OTP_OFF_CALIB_PWR5GM0 20
#define OTP_OFF_CALIB_RXGNOFF 24
#define OTP_OFF_CALIB_TXP_BOFF_2GH 28
#define OTP_OFF_CALIB_TXP_BOFF_2GL 29
#define OTP_OFF_CALIB_TXP_BOFF_5GH 30
#define OTP_OFF_CALIB_TXP_BOFF_5GL 31
#define OTP_OFF_CALIB_TXP_BOFF_V 32

/* MASKS to program bit fields in REGION_DEFAULTS register */
#define QSPI_KEY_FLAG_MASK ~(1U<<0)
#define MAC0_ADDR_FLAG_MASK ~(1U<<1)
#define MAC1_ADDR_FLAG_MASK ~(1U<<2)
#define CALIB_XO_FLAG_MASK ~(1U<<3)
#define CALIB_PDADJM7_FLAG_MASK ~(1U<<4)
#define CALIB_PDADJM0_FLAG_MASK ~(1U<<5)
#define CALIB_PWR2G_FLAG_MASK ~(1U<<6)
#define CALIB_PWR5GM7_FLAG_MASK ~(1U<<7)
#define CALIB_PWR5GM0_FLAG_MASK ~(1U<<8)
#define CALIB_RXGNOFF_FLAG_MASK ~(1U<<9)
#define CALIB_TXPOWBACKOFFT_FLAG_MASK ~(1U<<10)
#define CALIB_TXPOWBACKOFFV_FLAG_MASK ~(1U<<11)

/* OTP Device address definitions */
#define OTP_VOLTCTRL_ADDR 0x19004
Expand All @@ -335,7 +204,6 @@ struct rpu_mcu_boot_vectors {


#define OTP_RWSBMODE_ADDR 0x01B800
#define OTP_STANDBY_MODE 0x0
#define OTP_READ_MODE 0x1
#define OTP_BYTE_WRITE_MODE 0x42

Expand All @@ -351,8 +219,6 @@ struct rpu_mcu_boot_vectors {
#define OTP_TIMING_REG2_ADDR 0x01B824
#define OTP_TIMING_REG2_VAL 0x030D8B

#define PRODTEST_TRIM_LEN 15

#define OTP_FRESH_FROM_FAB 0xFFFFFFFF
#define OTP_PROGRAMMED 0x00000000
#define OTP_ENABLE_PATTERN 0x50FA50FA
Expand Down

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