Fault simulation

[Blebowski]

Hi,
just capturing an idea. @nickg as you are now working towards
Verilog implementation, it is likely that NVC will be able to parse a verilog
netlist soon (netlists usually contain only structural Verilog, so very small sub-set of the language).
It would be nice to try to simulate an input test pattern (e.g. in VCD or STIL),
and measure fault coverage obtained by such pattern.