Add fpga files

Makefile

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+default: openlane
+
+RTL = src/tt_um_tiny_shader_mole99.sv \
+      src/tiny_shader_top.sv \
+      src/shader_execute.sv \
+      src/shader_memory.sv \
+      src/spi_receiver.sv \
+      src/timing.sv \
+      src/synchronizer.sv
+
+FPGA_ICEBREAKER = fpga/rtl/icebreaker_top.sv
+
+FPGA_ULX3S = fpga/rtl/ulx3s_top.sv \
+	     fpga/rtl/pll40m.v
+
+# Simulation
+
+sim-icarus:
+	iverilog -g2012 -o top.vvp $(RTL) tb/tb_icarus.sv
+	vvp top.vvp -fst
+
+sim-icarus-gl:
+	iverilog -g2012 -s tb -o top.vvp $(GL) tb/tb_icarus_gl.sv -DUSE_POWER_PINS=1
+	vvp top.vvp -fst
+
+sim-verilator:
+	verilator --cc --exe --build -j 0 -Wall $(RTL) tb/tb_verilator.cpp -LDFLAGS "-lSDL2 -lpng16"
+	./obj_dir/Vtop
+
+sim-cocotb:
+	python3 tb/tb_cocotb.py
+
+# Software
+
+sw:
+	make -C sw/
+.PHONY: sw
+
+# FPGA
+
+# --- iCEBreaker ---
+
+synth-icebreaker: icebreaker.json
+
+build-icebreaker: icebreaker.bit
+
+upload-icebreaker: icebreaker.bit
+	openFPGALoader --board=ice40_generic -f icebreaker.bit
+
+icebreaker.json: $(RTL) $(FPGA_ICEBREAKER)
+	yosys -l $(basename $@)-yosys.log -DSYNTHESIS -DICEBREAKER -p 'synth_ice40 -top icebreaker_top -json $@' $^
+
+icebreaker.asc: icebreaker.json
+	nextpnr-ice40 --up5k --json $< \
+		--pcf fpga/constraints/icebreaker.pcf \
+		--package sg48 \
+		--asc $@
+
+icebreaker.bit: icebreaker.asc
+	icepack $< $@
+
+# --- ULX3S ---
+# TODO not tested!
+
+synth-ulx3s: ulx3s.json
+
+build-ulx3s: ulx3s.bit
+
+upload-ulx3s: ulx3s.bit
+	openFPGALoader --board=ulx3s -f ulx3s.bit
+
+ulx3s.json: $(RTL) $(FPGA_ULX3S)
+	yosys -l $(basename $@)-yosys.log -DSYNTHESIS -DULX3S -DMODE_800x600 -p 'synth_ecp5 -top ulx3s_top -json $@' $^
+
+ulx3s.config: ulx3s.json fpga/constraints/ulx3s_v20.lpf
+	nextpnr-ecp5 --85k --json $< \
+		--lpf fpga/constraints/ulx3s_v20.lpf \
+		--package CABGA381 \
+		--textcfg $@
+
+ulx3s.bit: ulx3s.config
+	ecppack $< $@ --compress
+
+clean:
+	rm -f *.vvp *.vcd
+	rm -f icebreaker.json icebreaker.asc icebreaker.bit icebreaker-yosys.log
+	rm -f ulx3s.json ulx3s.config ulx3s.bit ulx3s-yosys.log
+
+.PHONY: clean sim-icarus sim-verilator sim-cocotb sprites

fpga/constraints/icebreaker.pcf

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+# 12 MHz clock
+set_frequency  CLK        12
+set_io         CLK        35
+
+# RS232
+set_io -nowarn RX          6
+set_io -nowarn TX          9
+
+# LEDs and Button
+set_io -nowarn BTN_N      10
+set_io -nowarn LEDR_N     11
+set_io -nowarn LEDG_N     37
+
+# RGB LED Driver
+set_io -nowarn LED_RED_N  39
+set_io -nowarn LED_GRN_N  40
+set_io -nowarn LED_BLU_N  41
+
+# SPI Flash
+set_io -nowarn FLASH_SCK  15
+set_io -nowarn FLASH_SSB  16
+set_io -nowarn FLASH_IO0  14
+set_io -nowarn FLASH_IO1  17
+set_io -nowarn FLASH_IO2  12
+set_io -nowarn FLASH_IO3  13
+
+# PMOD 1A
+set_io -nowarn P1A1        4
+set_io -nowarn P1A2        2
+set_io -nowarn P1A3       47
+set_io -nowarn P1A4       45
+set_io -nowarn P1A7        3
+set_io -nowarn P1A8       48
+set_io -nowarn P1A9       46
+set_io -nowarn P1A10      44
+
+# PMOD 1B
+set_io -nowarn P1B1       43
+set_io -nowarn P1B2       38
+set_io -nowarn P1B3       34
+set_io -nowarn P1B4       31
+set_io -nowarn P1B7       42
+set_io -nowarn P1B8       36
+set_io -nowarn P1B9       32
+set_io -nowarn P1B10      28
+
+# PMOD 2
+set_io -nowarn P2_1       27
+set_io -nowarn P2_2       25
+set_io -nowarn P2_3       21
+set_io -nowarn P2_4       19
+set_io -nowarn P2_7       26
+set_io -nowarn P2_8       23
+set_io -nowarn P2_9       20
+set_io -nowarn P2_10      18
+
+# LEDs and Buttons (PMOD 2)
+set_io -nowarn LED1       27
+set_io -nowarn LED2       25
+set_io -nowarn LED3       21
+set_io -nowarn BTN2       19
+set_io -nowarn LED5       26
+set_io -nowarn LED4       23
+set_io -nowarn BTN1       20
+set_io -nowarn BTN3       18
+
+## 12-bit DVI Pmod on Pmod 1A/1B
+set_io -nowarn dvi_clk      38
+set_io -nowarn dvi_hsync    31
+set_io -nowarn dvi_vsync    28
+set_io -nowarn dvi_de       32
+set_io -nowarn dvi_r[0]     48
+set_io -nowarn dvi_r[1]      2
+set_io -nowarn dvi_r[2]      3
+set_io -nowarn dvi_r[3]      4
+set_io -nowarn dvi_g[0]     44
+set_io -nowarn dvi_g[1]     45
+set_io -nowarn dvi_g[2]     46
+set_io -nowarn dvi_g[3]     47
+set_io -nowarn dvi_b[0]     34
+set_io -nowarn dvi_b[1]     36
+set_io -nowarn dvi_b[2]     42
+set_io -nowarn dvi_b[3]     43