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Fixup
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@mole99
mole99 committed Apr 4, 2024
1 parent bdd1739 commit 82e139a
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2 changes: 2 additions & 0 deletions test/Makefile
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Expand Up @@ -32,6 +32,8 @@ COMPILE_ARGS += -DUNIT_DELAY=\#1
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v

export GL_TEST=1

# this gets copied in by the GDS action workflow
VERILOG_SOURCES += $(PWD)/gate_level_netlist.v

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