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Rearrange top signals
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mole99 committed Oct 27, 2023
1 parent af1e0fd commit a77e768
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Showing 3 changed files with 19 additions and 20 deletions.
2 changes: 1 addition & 1 deletion src/config.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@

# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
# Users have reported that values up to 0.8 worked well for them.
set ::env(PL_TARGET_DENSITY) 0.89
set ::env(PL_TARGET_DENSITY) 0.88

# CLOCK_PERIOD - Increase this in case you are getting setup time violations.
# The value is in nanoseconds, so 20ns == 50MHz.
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12 changes: 5 additions & 7 deletions src/top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -28,10 +28,7 @@ module top (
output logic hsync,
output logic vsync,
output logic next_vertical,
output logic next_frame,
output logic hblank,
output logic vblank,
output logic de
output logic next_frame
);

/*
Expand Down Expand Up @@ -81,7 +78,7 @@ module top (
};

/*
Timing
Horizontal and Vertical Timing
*/

logic signed [$clog2(HTOTAL) : 0] counter_h;
Expand All @@ -100,6 +97,9 @@ module top (
end
end
end

logic hblank;
logic vblank;

// Horizontal timing
timing #(
Expand Down Expand Up @@ -139,8 +139,6 @@ module top (
.counter (counter_v)
);

assign de = !(hblank || vblank);

logic [7:0] cur_time;
logic time_dir;

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25 changes: 13 additions & 12 deletions src/tt_um_top_mole99.sv
Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,12 @@ module tt_um_top_mole99 (
logic vsync;
logic next_vertical;
logic next_frame;
logic de;

// TODO async reset, sync deassert

top top_inst (
.clk (clk),
.reset_n (rst_n && ena),
.reset_n (rst_n && ena), // TODO save gate

// SPI signals
.spi_sclk (spi_sclk),
Expand All @@ -41,11 +42,8 @@ module tt_um_top_mole99 (
.rrggbb (rrggbb),
.hsync (hsync),
.vsync (vsync),
.next_vertical (next_vertical), // TODO v_pulse
.next_frame (next_frame),
.hblank (),
.vblank (),
.de (de)
.next_vertical (next_vertical),
.next_frame (next_frame)
);

logic [1:0] R;
Expand Down Expand Up @@ -78,18 +76,21 @@ module tt_um_top_mole99 (
// Bottom row
assign uio_out[4] = next_vertical; assign uio_oe[4] = 1'b1;
assign uio_out[5] = next_frame; assign uio_oe[5] = 1'b1;
assign uio_out[6] = de; assign uio_oe[6] = 1'b1;
assign uio_out[7] = 1'b0; /*TODO*/ assign uio_oe[7] = 1'b1;

assign uio_out[6] = 1'b0; assign uio_oe[6] = 1'b0; // - not used
assign uio_out[7] = 1'b0; assign uio_oe[7] = 1'b0; // - not used

// Input PMOD
// Input PMOD - not used

/*ui_in[0]
/*
ui_in[0]
ui_in[1]
ui_in[2]
ui_in[3]
ui_in[4]
ui_in[5]
ui_in[6]
ui_in[7]*/
ui_in[7]
*/

endmodule

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