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Significant Overhaul of the Interpreter's Timing Model #2235
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add cycles to the instruction execution time rather than the timestamp directly.
our understanding of how it works is just too incomplete to be worth implementing yet
undo previous commit because actually code cycles *do* matter
too slow, not accurate enough. we need to do a *lot* more research into the specifics of how this works with all the various aspects of the cpu's timings before we can make a good implementation
behavior seems to be a quirk of the way they made the interlock cycle mandatory
This reverts commit 764ee9e.
This reverts commit 789ef21.
comes with a small-ish performance hit
This reverts commit 587958e.
This reverts commit 0dc619d.
also ig add some comments next to the svc funcs so that someone searching for "swi" can find them easier
...i dont think this fixes anything
This reverts commit 443ecb3.
broke stuff
it's not bugged, it's also not inaccurate. something else is the issue...
it's faster...?
This reverts commit 45be951.
This reverts commit c90f10d.
main ram dma on the arm9 is officially fully operational.
gxfifo dma did not like that prior fix
Caused performance issues in games???
this probably fixes something
means they can fetch a word in the background while a word is still waiting to be read. Thanks Gericom!
apparently it completely broke sm64ds for some reason
This reverts commit 14c765d.
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Heavily reworks the ARM9 & ARM7 timing models to greatly improve accuracy (and slaughter performance).
Builds upon my work in #2125 and uses the excellent cache implementation found in #1955 (probably want to merge those two first). (hopefully building this pr upon those two doesn't cause any stupid or weird issues with git...? Fingers crossed?)
Implements:
Known Issues: