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[hw,prim,ram_1/2p] Add DFT response channel #25654

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[hw,prim,ram_1/2p] Add DFT response channel #25654

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ae93be8
[hw,prim,ram_1p] Add DFT response channel
Razer6 Dec 14, 2024
bcfd24b
[hw,prim,ram_2p] Add DFT response channel
Razer6 Dec 15, 2024
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6 changes: 6 additions & 0 deletions hw/ip/i2c/data/i2c.hjson
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Expand Up @@ -115,6 +115,12 @@
name: "ram_cfg"
act: "rcv"
}
{ struct: "ram_1p_cfg_rsp"
package: "prim_ram_1p_pkg"
type: "uni"
name: "ram_cfg_rsp"
act: "req"
}
{ struct: "logic"
type: "uni"
name: "lsio_trigger"
Expand Down
11 changes: 6 additions & 5 deletions hw/ip/i2c/doc/interfaces.md
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Expand Up @@ -16,11 +16,12 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:-------------|:----------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:-------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

Expand Down
8 changes: 5 additions & 3 deletions hw/ip/i2c/rtl/i2c.sv
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Expand Up @@ -12,9 +12,10 @@ module i2c
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int unsigned InputDelayCycles = 0
) (
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,

// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
Expand Down Expand Up @@ -98,6 +99,7 @@ module i2c
.clk_i,
.rst_ni,
.ram_cfg_i,
.ram_cfg_rsp_o,

.reg2hw,
.hw2reg,
Expand Down
60 changes: 31 additions & 29 deletions hw/ip/i2c/rtl/i2c_core.sv
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Expand Up @@ -8,35 +8,36 @@ module i2c_core import i2c_pkg::*;
#(
parameter int unsigned InputDelayCycles = 0
) (
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,

input i2c_reg_pkg::i2c_reg2hw_t reg2hw,
output i2c_reg_pkg::i2c_hw2reg_t hw2reg,

input scl_i,
output logic scl_o,
input sda_i,
output logic sda_o,

output logic lsio_trigger_o,

output logic intr_fmt_threshold_o,
output logic intr_rx_threshold_o,
output logic intr_acq_threshold_o,
output logic intr_rx_overflow_o,
output logic intr_controller_halt_o,
output logic intr_scl_interference_o,
output logic intr_sda_interference_o,
output logic intr_stretch_timeout_o,
output logic intr_sda_unstable_o,
output logic intr_cmd_complete_o,
output logic intr_tx_stretch_o,
output logic intr_tx_threshold_o,
output logic intr_acq_stretch_o,
output logic intr_unexp_stop_o,
output logic intr_host_timeout_o
input clk_i,
input rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,

input i2c_reg_pkg::i2c_reg2hw_t reg2hw,
output i2c_reg_pkg::i2c_hw2reg_t hw2reg,

input scl_i,
output logic scl_o,
input sda_i,
output logic sda_o,

output logic lsio_trigger_o,

output logic intr_fmt_threshold_o,
output logic intr_rx_threshold_o,
output logic intr_acq_threshold_o,
output logic intr_rx_overflow_o,
output logic intr_controller_halt_o,
output logic intr_scl_interference_o,
output logic intr_sda_interference_o,
output logic intr_stretch_timeout_o,
output logic intr_sda_unstable_o,
output logic intr_cmd_complete_o,
output logic intr_tx_stretch_o,
output logic intr_tx_threshold_o,
output logic intr_acq_stretch_o,
output logic intr_unexp_stop_o,
output logic intr_host_timeout_o
);

import i2c_reg_pkg::FifoDepth;
Expand Down Expand Up @@ -374,6 +375,7 @@ module i2c_core import i2c_pkg::*;
.clk_i,
.rst_ni,
.ram_cfg_i,
.ram_cfg_rsp_o,

.fmt_fifo_clr_i (i2c_fifo_fmtrst),
.fmt_fifo_depth_o (fmt_fifo_depth),
Expand Down
90 changes: 46 additions & 44 deletions hw/ip/i2c/rtl/i2c_fifos.sv
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Expand Up @@ -12,53 +12,54 @@ import i2c_reg_pkg::AcqFifoDepth;
localparam int unsigned FifoDepthW = $clog2(FifoDepth + 1),
localparam int unsigned AcqFifoDepthW = $clog2(AcqFifoDepth + 1)
) (
input logic clk_i,
input logic rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
input logic clk_i,
input logic rst_ni,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_o,

input logic fmt_fifo_clr_i,
output logic [FifoDepthW-1:0] fmt_fifo_depth_o,
input logic fmt_fifo_clr_i,
output logic [FifoDepthW-1:0] fmt_fifo_depth_o,
// FMT FIFO: writes controlled by CSR
input logic fmt_fifo_wvalid_i,
output logic fmt_fifo_wready_o,
input logic fmt_fifo_wvalid_i,
output logic fmt_fifo_wready_o,
input logic [FMT_FIFO_WIDTH-1:0] fmt_fifo_wdata_i,
// FMT FIFO: reads controlled by FSM
output logic fmt_fifo_rvalid_o,
input logic fmt_fifo_rready_i,
output logic [FMT_FIFO_WIDTH-1:0] fmt_fifo_rdata_o,
output logic fmt_fifo_rvalid_o,
input logic fmt_fifo_rready_i,
output logic [FMT_FIFO_WIDTH-1:0] fmt_fifo_rdata_o,

input logic rx_fifo_clr_i,
output logic [FifoDepthW-1:0] rx_fifo_depth_o,
input logic rx_fifo_clr_i,
output logic [FifoDepthW-1:0] rx_fifo_depth_o,
// RX FIFO: writes controller by FSM
input logic rx_fifo_wvalid_i,
output logic rx_fifo_wready_o,
input logic [RX_FIFO_WIDTH-1:0] rx_fifo_wdata_i,
input logic rx_fifo_wvalid_i,
output logic rx_fifo_wready_o,
input logic [RX_FIFO_WIDTH-1:0] rx_fifo_wdata_i,
// RX FIFO: reads controlled by CSR
output logic rx_fifo_rvalid_o,
input logic rx_fifo_rready_i,
output logic [RX_FIFO_WIDTH-1:0] rx_fifo_rdata_o,
output logic rx_fifo_rvalid_o,
input logic rx_fifo_rready_i,
output logic [RX_FIFO_WIDTH-1:0] rx_fifo_rdata_o,

input logic tx_fifo_clr_i,
output logic [FifoDepthW-1:0] tx_fifo_depth_o,
input logic tx_fifo_clr_i,
output logic [FifoDepthW-1:0] tx_fifo_depth_o,
// TX FIFO: writes controlled by CSR
input logic tx_fifo_wvalid_i,
output logic tx_fifo_wready_o,
input logic [TX_FIFO_WIDTH-1:0] tx_fifo_wdata_i,
input logic tx_fifo_wvalid_i,
output logic tx_fifo_wready_o,
input logic [TX_FIFO_WIDTH-1:0] tx_fifo_wdata_i,
// TX FIFO: reads controlled by FSM
output logic tx_fifo_rvalid_o,
input logic tx_fifo_rready_i,
output logic [TX_FIFO_WIDTH-1:0] tx_fifo_rdata_o,
output logic tx_fifo_rvalid_o,
input logic tx_fifo_rready_i,
output logic [TX_FIFO_WIDTH-1:0] tx_fifo_rdata_o,

input logic acq_fifo_clr_i,
output logic [AcqFifoDepthW-1:0] acq_fifo_depth_o,
input logic acq_fifo_clr_i,
output logic [AcqFifoDepthW-1:0] acq_fifo_depth_o,
// ACQ FIFO: writes controlled by FSM
input logic acq_fifo_wvalid_i,
output logic acq_fifo_wready_o,
input logic [ACQ_FIFO_WIDTH-1:0] acq_fifo_wdata_i,
input logic acq_fifo_wvalid_i,
output logic acq_fifo_wready_o,
input logic [ACQ_FIFO_WIDTH-1:0] acq_fifo_wdata_i,
// ACQ FIFO: reads controlled by CSR
output logic acq_fifo_rvalid_o,
input logic acq_fifo_rready_i,
output logic [ACQ_FIFO_WIDTH-1:0] acq_fifo_rdata_o
output logic acq_fifo_rvalid_o,
input logic acq_fifo_rready_i,
output logic [ACQ_FIFO_WIDTH-1:0] acq_fifo_rdata_o
);

// RAM synthesis parameters
Expand Down Expand Up @@ -290,16 +291,17 @@ import i2c_reg_pkg::AcqFifoDepth;
) u_ram_1p (
.clk_i,
.rst_ni,
.req_i (ram_req),
.write_i (ram_write),
.addr_i (ram_addr),
.wdata_i (ram_wdata),
.wmask_i ('1),
.rdata_o (ram_rdata),
.rvalid_o(ram_rvalid),
.rerror_o(/* unused */),
.cfg_i (ram_cfg_i),
.alert_o (/* unused */)
.req_i (ram_req),
.write_i (ram_write),
.addr_i (ram_addr),
.wdata_i (ram_wdata),
.wmask_i ('1),
.rdata_o (ram_rdata),
.rvalid_o (ram_rvalid),
.rerror_o (/* unused */),
.cfg_i (ram_cfg_i),
.cfg_rsp_o(ram_cfg_rsp_o),
.alert_o (/* unused */)
);
assign {ram_write, ram_addr, ram_wdata} = ram_arb_oup_data;

Expand Down
20 changes: 19 additions & 1 deletion hw/ip/otbn/data/otbn.hjson
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Expand Up @@ -163,9 +163,27 @@
{ struct: "ram_1p_cfg",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg",
name: "ram_cfg_imem",
act: "rcv"
},
{ struct: "ram_1p_cfg",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg_dmem",
act: "rcv"
},
{ struct: "ram_1p_cfg_rsp",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg_rsp_imem",
act: "req"
},
{ struct: "ram_1p_cfg_rsp",
package: "prim_ram_1p_pkg",
type: "uni",
name: "ram_cfg_rsp_dmem",
act: "req"
},

// Lifecycle escalation
{ struct: "lc_tx"
Expand Down
27 changes: 15 additions & 12 deletions hw/ip/otbn/doc/interfaces.md
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Expand Up @@ -10,18 +10,21 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------|:----------------------------|:--------|:------|--------:|:--------------|
| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | req | 1 | |
| edn_rnd | edn_pkg::edn | req_rsp | req | 1 | |
| edn_urnd | edn_pkg::edn | req_rsp | req | 1 | |
| idle | prim_mubi_pkg::mubi4 | uni | req | 1 | |
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
| keymgr_key | keymgr_pkg::otbn_key_req | uni | rcv | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:-----------------|:--------------------------------|:--------|:------|--------:|:--------------|
| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | req | 1 | |
| edn_rnd | edn_pkg::edn | req_rsp | req | 1 | |
| edn_urnd | edn_pkg::edn | req_rsp | req | 1 | |
| idle | prim_mubi_pkg::mubi4 | uni | req | 1 | |
| ram_cfg_imem | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_dmem | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp_imem | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| ram_cfg_rsp_dmem | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
| keymgr_key | keymgr_pkg::otbn_key_req | uni | rcv | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

Expand Down
5 changes: 4 additions & 1 deletion hw/ip/otbn/dv/uvm/tb.sv
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Expand Up @@ -108,7 +108,10 @@ module tb;
.lc_rma_req_i (escalate_if.req),
.lc_rma_ack_o (escalate_if.ack),

.ram_cfg_i('0),
.ram_cfg_imem_i('0),
.ram_cfg_dmem_i('0),
.ram_cfg_rsp_imem_o(),
.ram_cfg_rsp_dmem_o(),

.clk_edn_i (edn_clk),
.rst_edn_ni(edn_rst_n),
Expand Down
2 changes: 2 additions & 0 deletions hw/ip/otbn/dv/verilator/otbn_top_sim.sv
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Expand Up @@ -276,6 +276,7 @@ module otbn_top_sim (
.raddr_o ( ),
.rerror_o ( ),
.cfg_i ( '0 ),
.cfg_rsp_o ( ),

.wr_collision_o ( ),
.write_pending_o ( ),
Expand Down Expand Up @@ -321,6 +322,7 @@ module otbn_top_sim (
.raddr_o ( ),
.rerror_o ( ),
.cfg_i ( '0 ),
.cfg_rsp_o ( ),

.wr_collision_o ( ),
.write_pending_o ( ),
Expand Down
27 changes: 16 additions & 11 deletions hw/ip/otbn/rtl/otbn.sv
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Expand Up @@ -51,7 +51,10 @@ module otbn
output lc_ctrl_pkg::lc_tx_t lc_rma_ack_o,

// Memory configuration
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_imem_i,
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_dmem_i,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_imem_o,
output prim_ram_1p_pkg::ram_1p_cfg_rsp_t ram_cfg_rsp_dmem_o,

// EDN clock and interface
input clk_edn_i,
Expand Down Expand Up @@ -351,11 +354,12 @@ module otbn
.wmask_i (imem_wmask),
.intg_error_i(locking),

.rdata_o (imem_rdata),
.rvalid_o(imem_rvalid),
.raddr_o (),
.rerror_o(),
.cfg_i (ram_cfg_i),
.rdata_o (imem_rdata),
.rvalid_o (imem_rvalid),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_imem_i),
.cfg_rsp_o(ram_cfg_rsp_imem_o),

.wr_collision_o (imem_wr_collision),
.write_pending_o (imem_wpending),
Expand Down Expand Up @@ -566,11 +570,12 @@ module otbn
.wmask_i (dmem_wmask),
.intg_error_i(locking),

.rdata_o (dmem_rdata),
.rvalid_o(dmem_rvalid),
.raddr_o (),
.rerror_o(),
.cfg_i (ram_cfg_i),
.rdata_o (dmem_rdata),
.rvalid_o (dmem_rvalid),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_dmem_i),
.cfg_rsp_o(ram_cfg_rsp_dmem_o),

.wr_collision_o (dmem_wr_collision),
.write_pending_o (dmem_wpending),
Expand Down
3 changes: 2 additions & 1 deletion hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
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Expand Up @@ -127,7 +127,8 @@ if (FpgaSram == 1) begin : g_sram_fpga
.b_wmask_i (r_sram_wmask ),
.b_rdata_o (r_sram_rdata ),

.cfg_i ('0)
.cfg_i ('0),
.cfg_rsp_o ()
);
end else begin : g_sram_ff
logic [SramDw-1:0] mem [2**SramAw];
Expand Down
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