[ibex,fpga] Apply Ibex FPGA patches

[nasahlpa]

This PR applies two patches on top of Ibex that fix the following two FPGA related issues:

• Use WordZeroVal instead of 0 for initializing the FPGA register file
• Use async reset when not using a DSP for the Ibex FPGA counter

A patch is needed because:

• Without these fixes the SecureIbex parameter cannot be used on CW340 - this is needed for some SiVal tests
• These patches only touch the FPGA implementation. If we would vendor in the changes, we would get additional RTL changes that also affect the ASIC

[vogelpi]

This looks good to me, thanks @nasahlpa !

For awareness, I am also tagging @andreaskurth and @moidx . We need this FPGA-only RTL changes to enable using the lockstep core on the CW340 board which is required for SiVal. This change is unique to the earlgrey_1.0.0 branch and we will do a different fix (without patches) on the master branch.

[moidx]

I believe we still don't have bitstream caching enabled for earlgrey_1.0.0. @a-will can provide details on how to enable this.

[a-will]

I believe we still don't have bitstream caching enabled for earlgrey_1.0.0. @a-will can provide details on how to enable this.

Bitstreams are being cached, it looks like. The only thing to avoid would be using the latest hacky reference. bitstreams_workspace.py is currently hard-coded to look at master/latest.txt in the bucket for that. In general, though, the default value of "HEAD" should be used from a git repo.

[vogelpi]

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv

[nasahlpa]

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv

[andreaskurth]

Just a note that this code relying on a pre-processor `define isn't generally correct, because the pre-processor would resolve the `define before elaboration resolves the parameterized if-else construct. However, this only affects Xilinx code (it's inside an `ifdef FPGA_XILINX) and @nasahlpa tested that this works as intended in Vivado.

On master a proper fix has been applied (#25458), but that would also modify ASIC RTL, which we don't allow on this branch.

[andreaskurth]

CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
CHANGE AUTHORIZED: hw/vendor/lowrisc_ibex/rtl/ibex_register_file_fpga.sv

This only changes FPGA logic; ASIC logic isn't affected.