Removed new lines

Signed-off-by: Marcelo Carvalho Faleiro de Almeida <[email protected]>

hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv

@@ -272,32 +272,26 @@ class cip_base_vseq #(
 
     rsp = tl_seq.rsp;
 
-    if(rsp != null) begin
-      if (!write) begin
-        data = rsp.d_data;
-        if (check_exp_data && !cfg.under_reset) begin
-          bit [BUS_DW-1:0] masked_data = data & compare_mask;
-          exp_data &= compare_mask;
-          `DV_CHECK_EQ(masked_data, exp_data, $sformatf("addr 0x%0h read out mismatch", addr))
-        end
-      end
-      if (check_rsp && !cfg.under_reset && tl_intg_err_type == TlIntgErrNone) begin
-        `DV_CHECK_EQ(rsp.d_error, exp_err_rsp,
-                    $sformatf("unexpected error response for addr: 0x%x", rsp.a_addr))
+    if (!write) begin
+      data = rsp.d_data;
+      if (check_exp_data && !cfg.under_reset) begin
+        bit [BUS_DW-1:0] masked_data = data & compare_mask;
+        exp_data &= compare_mask;
+        `DV_CHECK_EQ(masked_data, exp_data, $sformatf("addr 0x%0h read out mismatch", addr))
       end
-
-      // Expose whether the transaction ran and whether it generated an error. Note that we
-      // probably only want to do a RAL update if it ran and caused no error.
-      completed = rsp.rsp_completed;
-      saw_err = rsp.d_error;
-
-    end else begin
-      // Expose whether the transaction ran and whether it generated an error. Note that we
-      // probably only want to do a RAL update if it ran and caused no error.
-      completed = 0;
-      saw_err = 0;
-
     end
+    if (check_rsp && !cfg.under_reset && tl_intg_err_type == TlIntgErrNone) begin
+      `DV_CHECK_EQ(rsp.d_error, exp_err_rsp,
+                  $sformatf("unexpected error response for addr: 0x%x", rsp.a_addr))
+    end
+    // Expose whether the transaction ran and whether it generated an error. Note that we
+    // probably only want to do a RAL update if it ran and caused no error.
+    completed = rsp.rsp_completed;
+    saw_err = rsp.d_error;
+    // Expose whether the transaction ran and whether it generated an error. Note that we
+    // probably only want to do a RAL update if it ran and caused no error.
+    completed = 0;
+    saw_err = 0;
   endtask
 
   // CIP spec indicates all comportable IPs will have the same standardized interrupt csrs. We can
@@ -729,9 +723,6 @@ class cip_base_vseq #(
       bit ongoing_reset;
       bit do_read_and_check_all_csrs;
       bit vseq_done = 1'b0;
-
-
-
       `uvm_info(`gfn, $sformatf("running run_seq_with_rand_reset_vseq iteration %0d/%0d",
                                 i, num_times), UVM_LOW)
       // Arbitration: requests at highest priority granted in FIFO order, so that we can predict
@@ -799,12 +790,9 @@ class cip_base_vseq #(
           // signal is de-asserted. To make things easier to debug if it hasn't done, fail in an
           // understandable way here.
           if (cfg.can_reset_with_csr_accesses) `DV_CHECK_FATAL(vseq_done)
-
           `uvm_info(`gfn, $sformatf("\nStress w/ reset is done for run %0d/%0d", i, num_times),
                     UVM_HIGH)
-
           disable fork;
-
           // delay to avoid race condition when sending item and checking no item after reset occur
           // at the same time
           #1ps;

hw/dv/sv/dv_lib/dv_base_sequencer.sv

@@ -20,16 +20,11 @@ class dv_base_sequencer #(type ITEM_T     = uvm_sequence_item,
 
   CFG_T cfg;
 
-
   `uvm_component_new
 
   function void build_phase(uvm_phase phase);
     super.build_phase(phase);
     if (cfg.has_req_fifo) req_analysis_fifo = new("req_analysis_fifo", this);
     if (cfg.has_rsp_fifo) rsp_analysis_fifo = new("rsp_analysis_fifo", this);
   endfunction : build_phase
-
-
-
-
 endclass

hw/ip/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv

@@ -21,14 +21,11 @@ class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq;
       logic [TL_DW-1:0] csr_val;
 
       `DV_CHECK_RANDOMIZE_FATAL(this)
-
       //Skip if a reset is ongoing...
       if (!cfg.clk_rst_vif.rst_n) return;
       // Insert some random delay
       cfg.clk_rst_vif.wait_clks_or_rst(delay);
 
-
-
       randcase
         // drive new gpio data in
         1: begin : drive_thread_data_in

hw/ip/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv

@@ -23,13 +23,11 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq;
     for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin
       string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)};
 
-
       //Skip if a reset is ongoing...
       if (!cfg.clk_rst_vif.rst_n) return;
       `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)
       cfg.clk_rst_vif.wait_clks_or_rst(delay);
 
-
       randcase
         // drive new gpio data in
         1: begin : drive_gpio_data_in
@@ -95,7 +93,6 @@ class gpio_intr_rand_pgm_vseq extends gpio_base_vseq;
       // Read interrupt state register value
       begin
         bit [TL_DW-1:0] reg_rd_data;
-
         //Skip if a reset is ongoing...
         if (!cfg.clk_rst_vif.rst_n) break;
         `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)

hw/ip/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv

@@ -31,14 +31,12 @@ class gpio_smoke_vseq extends gpio_base_vseq;
     `DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans)
     `uvm_info(`gfn, $sformatf("No. of transactions (gpio_i) = %0d", num_trans), UVM_LOW)
 
-
     for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin
       bit [TL_DW-1:0] csr_rd_val;
       string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)};
       `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_i)
       `uvm_info(msg_id, $sformatf("gpio_i = %0h", gpio_i), UVM_LOW)
 
-
       cfg.gpio_vif.drive(gpio_i);
 `ifdef GPIO_ASYNC_ON
       // If the CDC synchronizer prims are instantiated, it takes 2-3 cycles longer for inputs
@@ -68,7 +66,6 @@ class gpio_smoke_vseq extends gpio_base_vseq;
       logic [NUM_GPIOS-1:0] obs_gpio_o;
       string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)};
 
-
       //Skip if a reset is ongoing...
       if (!cfg.clk_rst_vif.rst_n) return;