Skip to content

[dv] Add ROT_AUTH configuration test. #3682

[dv] Add ROT_AUTH configuration test.

[dv] Add ROT_AUTH configuration test. #3682

Re-run triggered December 20, 2024 20:54
Status Failure
Total duration 41m 19s
Artifacts 34

ci.yml

on: pull_request
Earl Grey for CW340  /  Build bitstream
1m 56s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
2m 12s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
2m 0s
Earl Grey for CW310 / Build bitstream
Lint (slow)
11m 57s
Lint (slow)
Build documentation
4m 19s
Build documentation
Airgapped build
12m 40s
Airgapped build
Verible lint
1m 46s
Verible lint
Run OTBN smoke Test
2m 29s
Run OTBN smoke Test
Run OTBN crypto tests
20m 19s
Run OTBN crypto tests
Verilated English Breakfast
7m 38s
Verilated English Breakfast
Verilated Earl Grey
1h 25m
Verilated Earl Grey
CW305's Bitstream
22m 8s
CW305's Bitstream
Build Docker Containers
2m 37s
Build Docker Containers
Build and test software
13m 4s
Build and test software
CW340 Test ROM Tests  /  FPGA test
59s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
57s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
59s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
6m 6s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
1m 6s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
40m 30s
CW340 Manufacturing Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
35m 11s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
42m 10s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
39m 21s
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
16m 14s
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
6m 33s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
30m 49s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
4m 35s
CW310 ROM_EXT Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
27s
Verify FPGA jobs
Fit to window
Zoom out
Zoom in

Annotations

4 errors
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 127.
CW340 Manufacturing Tests / FPGA test
Process completed with exit code 3.

Artifacts

Produced during runtime
Name Size
execute_manuf_fpga_tests_cw340-targets
597 Bytes
execute_manuf_fpga_tests_cw340-test-results
63.9 KB