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[SiVal] Map manufacture tests to the testplans #3609

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[SiVal] Map manufacture tests to the testplans

[SiVal] Map manufacture tests to the testplans #3609

Re-run triggered December 18, 2024 22:42
@engdoreisengdoreis
#25698
engdoreis:manuf_tests
Status Success
Total duration 38m 48s
Artifacts 32

ci.yml

on: pull_request
Lint (quick)
3m 34s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 49s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1m 53s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
1m 51s
Earl Grey for CW310 / Build bitstream
Lint (slow)
11m 59s
Lint (slow)
Build documentation
5m 4s
Build documentation
Airgapped build
10m 44s
Airgapped build
Verible lint
1m 2s
Verible lint
Run OTBN smoke Test
2m 40s
Run OTBN smoke Test
Run OTBN crypto tests
22m 59s
Run OTBN crypto tests
Verilated English Breakfast
8m 5s
Verilated English Breakfast
Verilated Earl Grey
1h 16m
Verilated Earl Grey
CW305's Bitstream
21m 50s
CW305's Bitstream
Build Docker Containers
2m 46s
Build Docker Containers
Build and test software
14m 48s
Build and test software
CW310 SiVal Tests  /  FPGA test
26m 53s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
41m 15s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
32m 13s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 30s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
1m 6s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
7m 22s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
20m 16s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 56s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
44m 49s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
3m 52s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
38m 7s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
5m 58s
CW310 ROM_EXT Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
23s
Verify FPGA jobs
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Annotations

8 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
execute_rom_fpga_tests_cw310-targets
1.75 KB
execute_rom_fpga_tests_cw310-test-results
45.6 KB